https://doi.org/10.6113/JPE.2019.19.6.1351

ISSN(Print): 1598-2092 / ISSN(Online): 2093-4718

Two Modified Z-Source Inverter Topologies - Solutions to Start-Up Dc-Link Voltage Overshoot and Source Current Ripple

Dave Heema Bharatkumar^†, Dheerendra Singh^*, and Hari Om Bansal^*

^†,*Department of Electrical and Electronics Engineering, Birla Institute of Technology and Science, Pilani, India

Abstract

This paper proposes two modified Z-source inverter topologies, namely an embedded L-Z-source inverter (EL-ZSI) and a coupled inductor L-Z source inverter (CL-ZSI). The proposed topologies offer a high voltage gain with a reduced passive component count and reduction in source current ripple when compared to conventional ZSI topologies. Additionally, they prevent overshoot in the dc-link voltage by suppressing heavy inrush currents. This feature reduces the transition time to reach the peak value of the dc-link voltage, and reduces the risk of component failure and overrating due to the inrush current. EL-ZSI and CL-ZSI possess all of the inherent advantages of the conventional L-ZSI topology while eliminating its drawbacks. To verify the effectiveness of the proposed topologies, MATLAB/Simulink models and scaled down laboratory prototypes were constructed. Experiments were performed at a low shoot through duty ratio of 0.1 and a modulation index as high as 0.9 to obtain a peak dc-link voltage of 53 V. This paper demonstrates the superiority of the proposed topologies over conventional ZSI topologies through a detailed comparative analysis. Moreover, experimental results verify that the proposed topologies would be advantageous for renewable energy source applications since they provide voltage gain enhancement, inrush current, dc-link voltage overshoot suppression and a reduction of the peak to peak source current ripple.

Key words: Coupled inductor, Current ripple, Split voltage sources, Voltage gain, Voltage overshoot, Z-source inverter

Manuscript received Nov. 26, 2018; accepted Jun. 11, 2019

Recommended for publication by Associate Editor Honnyong Cha.

^†Corresponding Author: p2015407@pilani.bits-pilani.ac.in Tel: +91-9549451462, Birla Institute of Technology and Science

^*Department of Electrical and Electronics Engineering, Birla Institute of Technology and Science, Pilani, India

Ⅰ. INTRODUCTION

Recently, the research field of power electronics converters has seen a spurt in the exploration of impedance source inverter (ZSI) topologies. Table I shows a critical literature review of ZSI topological improvements. Despite its advantages over conventional VSI, the classical ZSI [1] shown in Fig. 1(a) suffers from a number of drawbacks. These drawbacks include: 1) lower voltage gain, 2) start-up inrush current, 3) discontinuous input current, 4) different grounds of the input dc source and the dc link, 5) ripple content in the source current, and 6) higher source voltage stress on the components. The quasi Z-source inverter (q-ZSI) [2], shown in Fig. 1(b), and the embedded Z-source inverter (E-ZSI) [3] both provided a continuous input current and a reduced source voltage stress. The q-ZSI topology in [4] used a coupled inductor in its Z network to eliminate source current ripple. However, all of these topologies have the same voltage gain as the original ZSI. Extended boost topologies have been proposed to enhance the voltage gain of ZSI /q-ZSI. The SL-ZSI [5] shown in Fig. 1(c) enhanced the voltage gain by replacing the inductors in the impedance network of the ZSI with switched inductor (SL) cells.

TABLE I CHARACTERISTICS OF VARIOUS ZSI/Q-ZSI TOPOLOGICAL IMPROVEMENTS

Topology	Structural Change	Remarks
q-ZSI	Change in the position of the input diode.	· Continuous input current. · Lower source current ripple. · No change in the voltage gain. · No. of passive components same as classical ZSI.
E-ZSI	Two split isolated dc sources placed in series with the inductors of Z network.
Bidirectional coupled inductor-based q-ZSI	Input diode replaced by the active switch and coupled inductor is used in qZ network.
Switched Inductor (SL)/Switched Capacitor (SC) Cell-Based Topologies
SL-ZSI	Inductors of the Z network are replaced by SL cells.	· Discontinuous as well as continuous current topologies. · Decreased capacitor voltage stress. · Decreased inductor current ripple content. · Increased voltage gain. · Increased number of passive components.
One cell SL-qZSI	One inductor of qZ network is replaced by SL cell.
rSL-qZSI; cSL-qZSI	Both the inductors in the qZ network are replaced by SL cell and placement of input source is changed in cSL-q-ZSI.
rESL-ZSI; cESL-ZSI	SL cells are used in place of inductors in the basic circuit of E-ZSI as well as input source placement in changed.
Improved SL-q-ZSI	One of the inductors in q-ZSI is replaced by hybrid SC/SL cell
MTSL-q-ZSI	Inductors in the cSL-q-ZSI are replace by SL and hybrid SC/SL cells
ESL-q-ZSI; iESL-q-ZSI	New structure of SC/SL hybrid cell is proposed and inductors in cSL-q-ZSI are replaced along with change in input source placement.
Switched Coupled Inductor-Based Topologies
SCL-q-ZSI	Use of three winding coupled inductor in improved SL-q-ZSI	· Increased voltage gain. · Lower number of passive components. · Lower inductor size · Issue with the leakage inductance.
mSSCL / mTSCL-qZSN;	Use of coupled inductors in the qZ network based SBI
T-source inverter (TSI)	Alternative LC networks are used with coupled inductors
trans-ZSI	Combination of a transformer and capacitor is used in basic Z network circuit
Y-source Z network	Z network with a coupled three winding transformer and a capacitor is used
∆-Source Z Network	Delta connected three winding coupled inductor is used in Z network
Extended Boost Topologies
Diode /capacitor assisted q-ZSI	Addition of more passive components like inductor, capacitor and diode is done to extend the Z network	· Very high voltage gain · Very high passive component count · Expandable networks · Increased switching loss
ZSI With Switched Z networks	Two Z networks are combined to form an alternate switching circuit
q-ZSI With Switched qZ Networks	Two qZ networks are combined to form an alternative switching circuit
ASC /SL-q-ZSI; q-ZSI With an Active Switched Z-Network	Active switch is included in the qZ network for switching between two qZ networks
AS-q-ZSI; EAS-q-ZSI	Active switch is added to the qZ network formed by using SL cell
Switched Boost ZSI /q-ZSI Topologies
q-SBI	Use of a single LC pair and an active switch to from a voltage boost up circuit	· Increased voltage gain. · Lower component count · Increased active switch count · Increased switching loss
rASLB /cASLB-qZSI	A family of high-boost-quasi-Z-source inverters (qZSIs) with combined active SL boost network.
Half /Full Bridge SBI	A new pattern of Z network formed out of combination of passive and active components.
DC-q-ZSI; CC-q-ZSI	The improved voltage gain is achieved by adding one auxiliary switch and one diode without using additional passive components.
L-ZSI Topologies
L-ZSI	A novel ZSI which only contains inductors and diodes in Z-source network.	· Increased voltage gain. · Elimination of inrush current. · Higher voltage gain cannot be achieved without increased component count. · Very high ripple content in the inductor currents.
Improved L-ZSI	Derived from L-ZSI with addition of two switching devices, one diode and one capacitor.
Integrated dual output L-ZSI	Three-winding mutually coupled inductor-based L-ZSI.
ZS/q-ZS Network Based Multilevel Inverter Topologies
ZS /q-ZS based NPC multilevel inverter	Combination of ZS /q-ZS network with three level neutral point clamped inverter	· Used to obtain very high magnitude of voltage output. · Fault tolerance capability is introduced due to presence of Z network. · Component count is reduced by developing a single-phase topology.
ZS /q-ZS CMI	Combination of ZS /q-ZS network with three level neutral point clamped inverter
Fault-Tolerant ZS /q-ZS CMI	Combination of ZS /q-ZS network with the H-bridge module
Hybrid five level inverter	Combination of a novel modified quasi-Z-source (M-q-ZS) inverter with a single-phase symmetrical hybrid three-level inverter.

Fig. 1. Conventional topologies. (a) ZSI. (b) q-ZSI. (c) SL-ZSI. (d) SL-q-ZSI. (e) L-ZSI.

(a)

(b)

(c)

(d)

(e)

The SL-q-ZSI [6] shown in Fig. 1(d) replaced one inductor in the impedance network of a q-ZSI with an SL cell. In addition, it provided an increased voltage gain along with a continuous input current. However, the voltage gain factor is compromised when compared to the SL-ZSI. The SL-qZSI was modified in [7]-[11] to further improve the voltage gain and to reduce the inductor and source current ripple. However, these switched cell-based topologies suffer from an increased passive component count.

Topologies with magnetically coupled windings enhance the voltage gain without increasing the passive component count. A switched-coupled inductor (SCL) cell with three windings was used in a modified SL-qZSI (SCL-qZSI) in [12] to increase voltage gain and suppress the startup inrush current. To further increase the voltage gain and reduce the inductor size, mSSCL-qZSN and mTSCL-qZSN were proposed in [13]. Many coupled inductor-based topologies such as the T-source Z network [14], Trans-Z-source [15], ∆-source Z network [16] and Y-source Z network [17] have been proposed to obtain a reduced inductor size, a reduced current ripple and an increased voltage gain. Although these topological improvements can improve voltage gain at a lower component count, the use of coupled inductors presents the challenge of leakage inductance.

A switched boost inverter (SBI) [18] adds an active switch to the Z network, which reduces passive component. However, it has the same boost factor as a ZSI. A number of topologies have been proposed to improve the voltage gain of theclassical SBI. These topologies include rASLB-qZSI and cASLB-qZSI [19], half bridge and full bridge continuous current SBI topologies [20], and DC-qZSI and CC-qZSI [21]. Despite their advantages, these topologies increase the active component count, which affects the efficiency of the converter.

To extend the voltage gain ratio with a decreased capacitor voltage stress extended-boost/enhanced-boost ZSI [22] topologies were proposed. These topologies used cascaded Z-networks. The topology in [23] further improved the voltage gain of the topology in [22]. An enhanced boost q-ZSI with two switched impedance networks was proposed in [24]. Although these topologies improve the voltage gain, their passive component counts are high. To reduce the passive component count while retaining the properties of conventional extended-boost topologies, extended boost ZSI/q-ZSI topologies were proposed in [25], [26] and [27].

The ZS/q-ZS networks, when integrated with conventional multilevel inverters, inherit the merits of both and provides improved inverter reliability due to their short circuit immunity. Energy storage photovoltaic applications with high power ratings benefit a great deal from these topologies. ZS/q-ZS Neutral point clamped (NPC) inverters, and ZS/q- ZS cascaded multilevel inverters (CMI) are rapidly emerging areas of research. A space vector based three level REC- NPCZSI was proposed in [28]. It improves the harmonic performance and ease of implementation. Meanwhile the topology proposed in [29] reduces the second order voltage harmonics and current ripples in the CMI. The single stage three level q-ZS based NPCs in [30] reduce the passive component count. In addition, q-ZS CMIs that are beneficial to energy storage photovoltaic applications were proposed in [31] and [32]. The topologies in [33] and [34] add fault tolerant capabilities to classical multilevel inverters. Lately, the q-ZS based CMIs proposed in [35] and [36] provided a high voltage output at a lower total harmonic distortion.

Although the aforementioned topological improvements solved many of the drawbacks of classical ZSIs, a few inherent disadvantages of the ZSIs are often overlooked. These disadvantages include: 1) the larger volume, higher costs and reduced life span due to the capacitors in impedance source networks; 2) initial dc-link voltage overshoot due to inrush current; and 3) resonance in the impedance network, which results in large voltage and current surges. The L-Z-source inverter (L-ZSI) [37], shown in Fig. 1(e), was proposed to solve the issues of inrush current and resonance in Z networks. Hence, L-ZSI has been attracting the attention of a lot of researchers for various applications using renewable energy sources and HEV [38], [39]. Although the L-ZSI can limit inrush current and eliminate resonance, it still suffers from the high ripple contents in the source current and inductor currents.

Moreover, to increase the voltage gain without increasing the shoot through duty ratio, the L-ZSI requires an increased number of the passive components, which results in lower efficiency of the inverter topology.

To solve the above issues of the classical L-ZSI topology two topologies are proposed in this paper. These topologies are an embedded L-Z-source inverter (EL-ZSI) and a coupled inductor-based L-Z-source inverter (CL-ZSI). The EL-ZSI and CL-ZSI possess all of the advantages offered by classical L-ZSI. In addition, they reduce the ripple content of both the source current and the inductors of the SL structure when compared to the L-ZSI. Both of the proposed topologies demonstrate the effects of utilizing an embedded voltage source and coupled inductor as a solution to the issue of current ripple content. The CL-ZSI offers a higher voltage gain than some conventional ZSI/q-ZSI topologies with a lower number of passive components. Meanwhile, the EL- ZSI has a negligibly reduced gain factor but has reduced source voltage stress. ZSI topologies are advantageous for various applications such as EV/HEV [40], [41], motor control [42], renewable energy systems. The proposed topologies contribute to providing an attractive choice of inverter topologies for applications such as energy storage renewable energy source systems that demands ripple-free current operation to improve the life span of the energy storage system (battery) and high voltage gain with a reduced number of passive components.

The remainder of this paper is organized as follows. Section II presents the designs and operational analyses of the proposed topologies. Section III carries out an analysis of the effects of the voltage overshoot and current ripple content in terms of the performance of ZSI topologies. Section IV highlights the superiority of the proposed topologies over conventional topologies through a comparative analysis. Section V validates the derived topologies through MATLAB simulation results and laboratory prototype results. Finally, some conclusions are presented in Section VI.

Ⅱ. ANALYSIS OF THE PROPOSED TOPOLOGIES

This section analyzes both the EL-ZSI topology and the CL-ZSI topology in terms of states of operation and modes of conduction. ZSI topologies, in general, operate in two states, i.e. (a) shoot through state and (b) non-shoot through state. Similarly, since the structures of both of the proposed topologies consist of a DC-DC voltage boost circuit formed by a combination of inductors or/and capacitors, their performances are affected by continuous conduction mode (CCM) and discontinuous conduction mode (DCM) conditions [43]. Thus, CCM and DCM operations are also analyzed for both of the proposed topologies. This section is concluded by presenting inductor and capacitor design procedures for the proposed topologies based on the steady state equations derived in operational state analyses of the proposed topologies.

A. Operational Analysis of EL-ZSI

An equivalent circuit of the proposed EL-ZSI consists of an SL structure containing two inductors and , three diodes , and . The DC source voltage is split into two equally distributed isolated DC sources placed at two different positions as shown in Fig. 2(a).

Fig. 2. Equivalent circuit of the EL-ZSI topology. (a) Basic circuit. (b) During the shoot through state. (c) During the non-shoot through state.

(a)

(b)

(c)

1) Shoot through State: During this state of operation, the main inverter circuit is considered to be short circuited. The inductors and get charged from isolated DC sources in this mode of operation. The diodes and are forward biased, while is reverse biased in this operation state.

An equivalent circuit of the EL-ZSI in this state of operation is shown in the Fig. 2(b). The steady state equations of the voltages appearing across the respective inductors in this state of operation are as follows:

                         (1)

2) Non-shoot Through State: During this state of operation, the main inverter circuit is modeled as a current source as shown in the Fig. 2(c). The inductors and are discharged in this state and provide voltage boost operation.

In this state, the diodes and are reverse biased and the diode is forward biased. The governing steady state equations for inductor voltages are shown below:

            (2)

 gets charged from the DC source and the capacitor . In the steady state operation, the average inductor voltage for one complete switching cycle should be zero. Applying volt-second balance rule to (1) and (2) yields:

                             (3)

Here, is the peak dc-link voltage.

Thus, the voltage boost factor (B ) of the EL-ZSI topology is:

                                     (4)

B. Operational Analysis of CL-ZSI

An equivalent circuit of the proposed CL-ZSI topology consists of an SL structure replacing the diode with a small value capacitor in the structure of the L-ZSI topology. In addition, the inductors and used in the SL structure are coupled inductors instead of normal inductors. An equivalent circuit of the CL-ZSI topology is shown in Fig. 3(a).

Fig. 3. Equivalent circuit of the CL-ZSI topology. (a) Basic circuit. (b) During the shoot through state. (c) During the non-shoot through state.

(a)

(b)

(c)

1) Shoot through State: During this state of operation, the main inverter circuit is considered to be short circuited. The inductor and the diodes and are forward biased and the diode is reverse biased in this operation state. From the equivalent circuit of CL-ZSI shown in the Fig. 3(b), the steady state equation of the voltages appearing across the inductors in this operating state are:

             (5)

2) Non-shoot through State: During this state of operation, the main inverter circuit is modeled as a current source as shown in Fig. 3(c). The inductors and get discharged in this state and provide voltage boost operation. In this state, the diodes and are reverse biased and the diode is forward biased. The governing steady state equations for inductor voltages are given below:

         (6)

Thus, the steady state equation defining relationship between the peak dc-link voltage and the DC source voltage obtained by applying the volt-second balance principle is:

                              (7)

The voltage boost factor (B) of the CL-ZSI is:

                                          (8)

C. CCM and DCM Operation Analysis of the Proposed Topologies

The steady state equations (1)-(8) derived in the previous section for the proposed topologies, are valid only if the inverter topology operates in the CCM. In addition, the design of any ZSI topology should be done in such a way that the inverter always operates in the CCM in order to reduce the input voltage stress, which is an important feature required for power electronics applications. Since the basic impedance network of the proposed inverter topologies contains inductors, the operation of such inverters in the DCM can be avoided by appropriately calculating the value of inductors in the impedance network. In this section the derivation of the inductance value required for the CCM operation of the EL-ZSI and CL-ZSI topologies is demonstrated by explaining the procedure for one inductor, which can be replicated for all of the inductors present in the equivalent circuit of the proposed topologies. In addition, the change observed in the performance of the proposed circuits operated in the DCM is demonstrated by deriving the governing equations of operation in this mode.

Fig. 4. Inductor voltage and current waveforms. (a) EL-ZSI at the boundary condition of the CCM / DCM. (b) CL-ZSI at the boundary condition of the CCM / DCM. (c) EL-ZSI during DCM operation. (d) CL-ZSI during DCM operation.

(a)

(b)

(c)

(d)

As can be seen from Fig. 4(a) and (b), at the point where the operation of the inverter topologies is at the boundary of the CCM and the DCM operation, the average inductor current i_L is the function of the peak ripple current ∆i_L. Then, the generalized equation for the peak ripple current of the inductor is given as:

                                           (9)

Using (1) and (5) for the EL-ZSI and CL-ZSI topologies, the expression for the peak ripple inductor current for the inductor of both topologies is shown below.

The generalized expressions for the average inductor current at the boundary condition of operation are:

……. for EL-ZSI                                (10)

………for CL-ZSI                                 (11)

                                                   (12)

Using (10), (11) and (12) the average inductor currents flowing through in the EL-ZSI and CL-ZSI are:

…… for EL-ZSI                                (13)

…… for CL-ZSI                                (14)

Thus, if the average inductor current flowing through in the EL-ZSI and CL-ZSI is greater than (13) and (14), the operation of both topologies is in the CCM. The expression for designing for operation in the CCM is:

……. for EL-ZSI                               (15)

……. for CL-ZSI                               (16)

During the DCM operation, the steady state equations governing the operation of the proposed topologies do not hold true. As can be seen from Fig. 4(c) and (d), during the DCM operation the expressions of the average inductor current flowing through in the EL-ZSI and CL-ZSI are:

…                  (17)

      (18)

For an ideal inverter, let P be the inverter power rating, and be the load resistance. The general expression for the average inductor current flowing through the inverter is:

                                     (19)

Using (17), (18) and (19) the expressions governing the operation of the EL-ZSI and CL-ZSI during the DCM are given in (23) and (24) respectively as:

                (20)

       (21)

Equations (20) and (21) show that during the DCM operation, the steady state equations no longer govern the operation of the proposed inverters and the boost factor no longer depends simply on . Instead, the boost factor also depends on the loading conditions, switching frequency and value of the inductance.

Ⅲ. SIMPLE BOOST CONTROL OF THE PROPOSED TOPOLOGIES

There are three basic control methods [44] that are usually applied to impedance source inverter circuits. They are simple boost control, maximum boost control and constant boost control. For pulse width modulation control of the proposed inverter topologies, the simple boost control method is used. This method is implemented by comparing a straight line with an amplitude greater than or equal to the peak value of the three-phase references, in order to generate shoot through signals. The shoot through duty ratio of the PWM control is adjusted by changing the magnitude of the constant value. The relationship between the maximum duty cycle and the modulation index for the simple boost control (SBC) method is given by:

                                 (22)

Using (4), (8) and (22), the boost factor of the proposed inverter topologies can be derived in terms of as:

……for EL-ZSI                              (23)

……for CL-ZSI                               (24)

The peak phase voltage of the main inverter output is expressed as:

                (25)

The voltage gains of the proposed topologies are:

…. for EL-ZSI                        (26)

…. for CL-ZSI                       (27)

Fig. 5 represents the switching signals for all six switches of a three-phase inverter obtained by the SBC method.

Fig. 5. PWM generation using the simple boost control method.

Ⅳ. ANALYSIS OF THE ISSUES OF START-UP VOLTAGE OVERSHOOT AND CURRENT RIPPLE

The impedance network of any variant of ZSI topology consists of inductors and capacitors. Thus, it acts as an energy storage circuit and as a filter circuit for the main inverter circuit. The role of inductors is to provide a voltage boost in the non-shoot through state of operation and to limit current ripples. Meanwhile, capacitors absorb the current ripples of the conventional ZSI and SL-ZSI topologies. The dc-link capacitors, which are discharged during the shoot through state, come into direct contact with the DC source during the non-shoot through state. The initial voltage across the dc-link capacitors being zero, a heavy inrush current flows through the circuit charging the dc-link capacitors to a V_dc/2 voltage. In addition, the inductors and capacitors resonate, which generates spikes in the current and voltage. Due to this, the harmonic content increases and there is a voltage overshoot in dc-link voltage that is high enough to damage the circuit components. This phenomenon also increases the required ratings of the circuit components. Since the proposed topologies eliminate the use of dc-link capacitors, due to the fact that they are a variant of the L-ZSI topology, they also eliminate the cause of large inrush currents and start-up voltage overshoots. Simulation results of the dc-link voltage and inverter output voltage of the ZSI, SL-ZSI and the proposed topologies for , and are shown in Fig. 6(a) to (d). These results demonstrate the effectiveness of the proposed topologies over conventional topologies in terms of start-up voltage overshoot. As can be seen from Fig. 6(a) and (b), the dc-link voltage of the ZSI and the SL-ZSI topologies face the issue of start-up voltage overshoot. The value of the dc-link voltage rises to 115 V in the case of the ZSI and to 124 V in the case of the SL-ZSI. Meanwhile, according to the voltage boost factor of these respective topologies, their dc-link voltage for , and should be 62.5V for the ZSI topology and 78.57V for the SL-ZSI topology. This rise in the dc-link voltage also affects the inverter output voltage, which is load the voltage of the main inverter circuit. This is reflected in the waveforms shown in Fig. 6(a) and (b). In comparison to conventional topologies, the proposed topologies do not suffer from the issue of start-up voltage overshoot as shown in Fig. 6(c) and (d). In addition, the load voltage does not suffer from a rise in the voltage.

Fig. 6. Dc-link voltage and inverter output voltage for , and . (a) SL-ZSI. (b) ZSI. (c) EL-ZSI. (d) CL-ZSI.

(a)

(b)

(c)

(d)

Since the design of these topologies aims to serve renewable source-based applications, the ripple content of both the source current and the inductor current has become an important parameter of design. The L-ZSI topology also offers the advantage of eliminating dc-link capacitors. However, since dc-link capacitors help in absorbing inductor current ripples, the absence of these capacitors results in a large content of ripples in the inductor current of the L-ZSI topology. As shown in Fig. 7(a), to obtain a dc-link voltage with a magnitude of 61V, the average inductor current is 2.232A and the peak to peak ripple current is 0.4243A. Thus, the percentage of ripple current in the inductor is 19%, which is not an ideal for renewable energy source applications.

Fig. 7. Dc-link voltage and inductor current. (a) L-ZSI. (b) EL- ZSI. (c) CL-ZSI.

(a)

(b)

(c)

In the proposed topologies two different current ripple techniques have been implemented to decrease the ripple content of the source current and the inductor current. Thus, even though the dc-link capacitors are eliminated, the proposed topologies have negligible current ripple contents. The EL-ZSI topology utilizes an embedded source to reduce the current ripples. The placement of the DC source in series with the inductors of the SL structure reduces the ripple content of the source current and the inductor current. It also reduces the average current to be carried by the inductor. As can be seen from Fig. 7(b), for obtaining the same dc-link voltage 61V as mentioned above for the L-ZSI, the average inductor current in the EL-ZSI topology is 2.17A, and the peak to peak ripple current is 0.2125A, which is a 9.7% ripple content.

Similarly, in the CL-ZSI topology the concept of a coupled inductor is utilized to reduce the ripple content. Appropriately designed coupled inductors help in reducing the average inductor current and the peak to peak ripple current of the source current and the inductor current to 2.152A and 0.1364 A respectively, as shown in the Fig. 7(c). This turns out to be a 6.33% ripple content. When compared to the L-ZSI topology both of the proposed topologies reduce the current ripple content by more than 50%. In addition, when compared to other conventional ZSI topologies, the ripple content of the source current and inductor currents in the proposed topologies for the same value are quite low. This can be witnessed from Fig. 11(a) and 11(b).

Fig. 8. Voltage boost factor versus D_sh.

Fig. 9. Voltage gain versus D_sh.

Fig. 10. Comparative analysis. (a) Voltage gain versus the modulation index. (b) Capacitor voltage stress versus D_sh.

(a)

(b)

Fig. 11. Comparative analysis of the inductor current ripple factor. (a) For the inductor L1. (b) For the inductor L2.

(a)

(b)

Ⅴ. COMPARATIVE ANALYSIS OF THE PROPOSED TOPOLOGIES WITH THE CONVENTIONAL TOPOLOGIES

Fig. 8 shows a comparison of the proposed topologies and conventional topologies in terms of changes in the boost factor with changes in . As can be seen from the graph, the boost factor of the CL-ZSI is higher than most of the other topologies for various values of . Meanwhile, the boost factor of the EL-ZSI is a little smaller than those of the L-ZSI and the ZSI. Moreover, the variation in the boost factor i.e., the dc-link voltage with variation in , is very slow and linear. This helps in the design of the control system for the dc-link voltage since its control becomes easier.

Fig. 9 shows the variation in the voltage gain obtained through the proposed and conventional topologies with changes in . Unlike the conventional topologies, the voltage gains of the proposed topologies are independent of their , which is 2 for the CL-ZSI and 1 for the EL-ZSI.

Fig. 10(a) shows a comparison of the proposed and conventional topologies in terms of variation in the voltage gain with the modulation index. The voltage gain of the proposed topologies is also independent of the value of the modulation index. Fig. 10(b) shows a comparison of the change in the voltage stress on the capacitor with a change in. As in the conventional topologies, there is capacitor stress. In the L-ZSI and the EL-ZSI there is no capacitor voltage stress since no capacitors are present. Whereas in the CL-ZSI. In is not a dc-link capacitor. Instead, it is a part of the switched inductor structure. The stress on this capacitor in the CL-ZSI is lower than the voltage stress on the dc-link capacitor of any of the conventional topologies. In addition, it does not change with the change in . Instead, it is always the same as the DC source voltage.

Equations for the ripple in the source current of the proposed topologies can be obtained by deriving expressions of the ripple in the inductor currents of the switched inductor structure since they are both equal. The expression for the inductor voltage can be given as:

                                                  (28)

For the proposed topologies considering (1) and (5) for the EL- ZSI and the CL-ZSI topology respectively, the change in the current during shoot through state can be given as:

…  for EL-ZSI                                  (29)

… for CL-ZSI      &p;                            (30)

In the simple boost control method, two shoot through states occur in every one complete switching cycle of a time period . Thus, the time period for each shoot through state is . Using (4), (8), (29) and (30), during the shoot through state, the inductor current ripple for the EL-ZSI and the Cl-ZSI can be given as:

… for EL-ZSI             (31)

… for CL-ZSI            (32)

Similarly, for the non-shoot through state, the inductor current ripple expressions for the proposed topologies can be derived using (2), (6) and (28) as follows:

.. for EL-ZSI          (33)

..for CL-ZSI          (34)

Thus, from (31), (32), (33) and (34), it can be concluded that the current ripple in the shoot through state and the non-shoot through state is the same as it should be for the proposed topologies. Similarly, the expressions for the current ripple equations for the other inductors of the proposed topologies and the inductors of the conventional topologies can be derived. Fig. 11(a) and (b) show a comparison between the magnitude of the ripple content of the inductor currents at different values of , where are the inductor current ripple factors. These figures demonstrate that for a given value of, the ripple content in the inductor and source currents of the inductors in the switched structure of the proposed topologies are lower than all of the conventional topologies.

Table II compares the required value of the inductance by the conventional and the proposed topologies for the same boost factor value. It shows that the inductance value required by the CL-ZSI is much lower than all of the conventional topologies. while, that required by the EL-ZSI is slightly higher than that of the SL-ZSI topology. However, the SL-ZSI requires a minimum of 4 inductors, and the EL-ZSI requires a minimum of 2 inductors.

TABLE II DESIGN OF THE IMPEDANCE NETWORK INDUCTOR

Inductor Current Stress and Source Current Ripple
Parameter	ZSI	SL-ZSI	SL-q-ZSI	L-ZSI	EL-ZSI	CL-ZSI
L current stress
Source current ripple	High	High	Moderate	Very High	Negligible	Negligible
Inductance Value for B = 2
Inductance
Gain	1.5	1.77	2.038	1.35	1	2
Dsh.	0.25	0.15	0.19	0.35	0.5	0.03
Inductance value
where is defined as the ratio of the peak-to-peak inductor current ripple to the average current of the inductor and is the operating frequency, which is twice the switching frequency and is the average input source current.

Table III compares the proposed topologies and the conventional topologies in terms of various performance parameters such as the voltage boost factor, voltage gain, capacitor voltage stress, input diode voltage stress and required number of passive components.

TABLE III COMPARISON OF VARIOUS PERFORMANCE PARAMETERS

Comparison of Topology Characteristics
Parameter	ZS	SL-ZSI	SL-q-ZSI	L-ZSI	EL-ZSI	CL-ZSI
No. of components	L = 2, C = 2, D = 1	L = 4, C = 2, D =7	L = 3, C = 2, D = 4	L = 2, C = 0, D = 3	L= 2, C = 0, D = 3	L = 1 coupled inductor, C = 1, D= 2
Continuous input current	No	No	Yes	Yes	Yes	Yes
Startup inrush current	Yes	Yes	Yes	No	No	No
Common ground	No	No	Yes	Yes	Yes	Yes
Boost Factor, B
Gain, G					1	2
Comparison of The Voltage Stress in The Same Input DC Voltage and Shoot Through Duty Ratio
Cap. Volt. Stress,				NA	NA
Cap. Volt. Stress,				NA	NA	NA
dc-link voltage
Diode voltage Stress
	NA					NA
	NA
Inverter Switch Voltage stress
Comparison of The Current Stress in The Same Input DC Voltage, Voltage Gain and Loading Condition
Average dc-link current,
Input current,

Ⅵ. DERIVATION OF MATHEMATICAL AND MAGNETIC CONDITIONS FOR CURRENT RIPPLE CANCELLATION IN THE CL-ZSI

The inductor voltage during the shoot through operation state of the CL-ZSI according to (5) is:

                                    (35)

Similarly, during non-shoot through operation, the inductor voltages are given by (6) as:

               (36)

If the structures are considered symmetrical, the above equation can be represented as:

                       (37)

From (36) and (37) it can be concluded that the voltage across each of the inductors in the shoot through and non-shoot through states of operation are the same.

Considering the coupling between and , the inductors of the switched inductor structure of the CL-ZSI yield:

                              (38)

                              (39)

Here:

By considering the current ripples in an operating sequence, the equality between the inductor voltages of the inductors in each cell can be rewritten as follows:

                              (40)

                              (41)

Since the inductor voltages of and are equal for the shoot through and non-shoot through operations, the following can be obtained:

          (42)

Replacing the mutual inductances by M, and the self-inductances by , the above equation can be rewritten as:

                  (43)

                                     (44)

Thus, the necessary conditions for designing the coupled inductor so that it eliminates the ripples is:

                                                   (45)

Considering the above equations, the coupled inductor is designed using an EE-65 core with the parameters as mentioned in Table IV.

TABLE IV COUPLED INDUCTOR DESIGN PARAMETERS

Parameter	Value
Turns Ratio of Inductors	1:1
Inductance value	1mH (primary), 1mH (secondary)
Core type used for winding	EE-65 ferrite core
Position of winding on the core	Central limb
Mutual inductance, M	0.9mH
Coefficient of coupling (k)	0.9

Ⅶ. SIMULATION AND EXPERIMENTAL RESULTS

Table V presents the parameters used to obtain the simulation and experimental results.

TABLE V SIMULATION AND EXPERIMENTAL PARAMETERS

Parameters	EL-ZSI	CL-ZSI
dc-link voltage,	53 V	53 V
DC source voltage,	48 V	24 V
Shoot through duty ratio,	0.1	0.1
Modulation Index, M	0.9	0.9
Boost Factor, B	1.11	2.22
Inductor value,	1mH	1mH
Capacitor, (Nippon Chemi-Con)	-	470µF, 450 V
Diodes, MUR3060PT	600 V, 30 A	600 V, 30 A
3-phase resistive load	100Ω	100Ω

Fig. 12 (a) and (b) show the experimental setup for the CL- ZSI topology and the EL-ZSI topology, respectively. Fig. 13 and Fig. 14 show the simulation results and experimental results of the proposed topologies performed with the parameters mentioned in Table V. The simulation results and the experimental results are in good agreement with the theoretical expressions derived for the steady state performance of the proposed inverter topologies. For the parameters mentioned in Table V and for the performance parameters of = 0.1, = 0.9 and = 48V the dc-link voltage obtained in case of the EL-ZSI topology is 53V in the simulation environment and 52 V in the hardware prototype. Similarly, for the CL- ZSI topology, the obtained dc-link voltage is in agreement with expression (8), and has values of 53V and 52V in case of the simulation and the experiment, respectively. The above results can be witnessed from Fig. 13 (a) and Fig. 14 (a). As per expressions (1) and (5), the inductor voltages in case of both the EL-ZSI and the CL-ZSI for the above-mentioned performance parameters should be 24 V. This turns out to be 23 V and 22 V in case of the simulation and experimental performance respectively for both of the topologies. The peak inductor current obtained while validating the proposed topologies in the simulation environment are 2.054 A and 1.951 A for the EL-ZSI and the CL-ZSI, respectively. The peak to peak inductor currents, in the case of the EL-ZSI and the CL-ZSI, obtained in the simulation validation are 0.1945 A and 0.1205 A, respectively. The experimental prototyping has a slight variation since the obtained peak inductor currents are the same 2.05 A and 1.96 A for the EL-ZSI and the CL-ZSI, respectively. However, the peak to peak inductor currents are 0.2925 A and 0.1995 A. The experimental prototyping has a slight variation since the obtained peak inductor currents are the same 2.05 A and 1.96 A for the EL-ZSI and the CL-ZSI topology, respectively. However, the peak to peak inductor currents are 0.2925 A and 0.1995 A. The results for the inductor voltages and the inductor currents in the simulation and experimental performances can be witnessed from Fig. 13 (c) and (d) and Fig. 14 (c) and (d) for the EL-ZSI and the CL-ZSI topologies.

Fig. 12. Experimental setup. (a) CL-ZSI topology. (b) EL-ZSI topology.

(a)

(b)

Fig.13. Simulation results. (a) DC source voltage, dc-link voltage and line-line load voltage of the EL-ZSI. (b) DC source voltage, dc-link voltage and line-line load voltage of the CL-ZSI. (c) Inductor voltages and inductor currents of the EL-ZSI. (d) Inductor voltages and inductor currents of the CL-ZSI.

(a)

(b)

(c)

(d)

Fig.14. Experimental results. (a) DC source voltage, dc-link voltage and line-line load voltage of the EL-ZSI. (b) DC source voltage, dc-link voltage and line-line load voltage of the CL-ZSI. (c) Inductor voltages and inductor currents of the EL-ZSI. (d) Inductor voltages and inductor currents of the CL-ZSI.

(a)

(b)

(c)

(d)

Ⅷ. CONCLUSION

This paper proposed two improved inverter topologies named EL-ZSI and CL-ZSI. Both topologies are shown to be effective in solving the vital issues of start-up voltage overshoot and inductor current ripple content. Both topologies eliminate the dc-link voltage overshoot by eliminating the use of bulky dc-link capacitors, which also reduces the size of the inverter. The use of an embedded voltage source and coupled inductor is proposed to eliminate the current ripple content. The EL-ZSI has no additional passive elements except for its switched inductor structure. In addition, it reduces the current ripple content to as low as 15.63% of the average source current as can be seen from experimental results. However, in this case, the boost factor is slightly reduced, and the requirement of two isolated equal voltage sources limits its use in industrial applications. To overcome the limitations of the EL-ZSI, the CL-ZSI is proposed. The CL-ZSI improves the voltage boost factor, and further reduces the average inductor current level and current ripple content. Experimental results show that the CL-ZSI reduces the source current ripple to a value as low as 10.72% of the average source current for the same voltage gain. A comparative analysis with conventional topologies verifies the superiority of the proposed topologies in terms of overall performance. Simulation and experimental prototyping further validate this superiority.

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Dave Heema Bharatkumar was born in Morbi, India, in 1989. She received her B.S. degree in Electrical Engineering from the VVP Engineering College, Rajkot, India, in affiliation with the Gujarat Technological University, Ahmedabad, India, in 2012. She received her M.S. degree in Electrical Power Systems from RK University, Rajkot, India, in 2014. She is presently working as a Research Scholar in the Department of Electrical and Electronics Engineering, Birla Institute of Technology and Science, Pilani, India. Her current research interests include power electronics systems, the design and analysis of impedance source inverters, converter-based drive systems.

Dheerendra Singh was born in Uttar Pradesh, India, in 1969. He received his B.S. degree in Electrical Engineering from the Indian Institute of Technology Roorkee (IIT Roorkee), Uttar Pradesh, India; his M.S. degree in Energy Studies from the Indian Institute of Technology Delhi (IIT Delhi), Delhi, India; and his Ph.D. degree in Electrical Engineering from the Birla Institute of Technology and Science (BITS), Pilani, India. Since 1999, he has been with Department of Electrical and Electronics Engineering, BITS, where he is presently working as an Associate Professor. His current research interests include power quality, power electronics based renewable energy systems, modeling of power devices, and nano biosensors. 

Hari Om Bansal was born in Balahedi, India, in 1976. He received his B.S. degree in Electrical Engineering from Engineering College Kota, Kota, India, in 1998; his M.S. degree in Electrical Power System from Malviya Regional Engineering College, Jaipur, India, in 2000; and his Ph.D. degree in Electrical Engineering from the Birla Institute of Technology and Science (BITS), Pilani, India in 2005. In 2001, he became a Lecturer in the Department of Electrical and Electronics Engineering at BITS, where he was an Assistant Professor from 2006 to 2013, and has been an Associate Professor since 2013. His current research interests include control systems, power systems, renewable energy, hybrid electric vehicles and power quality compensation systems.