사각형입니다.

https://doi.org/10.6113/JPE.2019.19.6.1393

ISSN(Print): 1598-2092 / ISSN(Online): 2093-4718



Power Flow Control of Four Channel Resonant Step-Down Converters


Lilla Litvani* and Janos Hamar


†,*Dept. of Automation and Applied Informatics, Budapest University of Technology and Economics, Budapest, Hungary



Abstract

This paper proposes a new power flow control method for soft-switched, four channel, five level resonant buck dc-dc converters. These converters have two input channels, which can be supplied from sources with identical or different voltages, and four output channels with arbitrary output voltages. They are specially designed to supply multilevel inverters. The design methodology for their power flow control has been developed considering a general case when the input voltages, output voltages and loads can be asymmetrical. A special emphasize is paid to the limitations and restrictions of operation. The theoretical studies are confirmed by numerical simulations and laboratory tests carried out at various operation points. Exploiting the advantages of the newly proposed power control strategy, the converter can supply five level inverters in dc microgrids, active filters, power factor correctors and electric drives. They can also play an interfacing role in renewable energy systems.


Key words: Design, Multichannel converter, Power flow control, Resonant converter, Soft switching, Step-down dc-dc converter


Manuscript received Feb. 6, 2019; accepted Jun. 27, 2019

Recommended for publication by Associate Editor Jae-Beum Lee.

Corresponding Author: litvani.lilla@aut.bme.hu Tel: +36 (1) 463-2337, Budapest University of Technology and Economics

*Dept. Autom. Applied Inform., Budapest Univ. Tech. Economics, Hungary



Ⅰ. INTRODUCTION

Resonant DC/DC converters have recently drawn a lot of attention in various application fields due to their specific advantages. Among these advantages, zero voltage and zero current switching (ZVS and ZCS), high efficiency, low electromagnetic interference (EMI), improved performance and high power density make them popular in DC microgrids, renewable energy systems and switched mode power supplies. Several papers have been published on different converter topologies for electric vehicles [1]-[3]. In fuel cells, beside a simple control, the power semiconductors require a low voltage stress, while the DC bus needs a higher constant voltage. In order to achieve this, a three-level, H-type structural boost converter was created to provide a wide voltage-gain range [4]. For DC microgrid applications, voltage-balancing and battery state of charge adjusting are important requirements for an applied converter. Several control strategies have been proposed to ensure these criteria [5], [6]. For battery charging applications, a high efficiency design method has been proposed, where lithium-ion battery cells have been used due to their high current and voltage rates, which results in a high power density [7]. A parameter selection method was proposed to implement multi-element resonant converters after four design steps. The achieved converter allowed for an efficiency as high as 96.9% [8].

Since the application field of DC/DC converters is so wide, several different topologies have been presented with various additional advantages. Zero-voltage and zero-current switching topologies allow for a decrease of the switching losses [9]- [11]. In addition to ZVS, voltage regulation can be reached over a wide range of loads by the hybrid control of the frequency and duty ratio, which results in an enlarged conversion efficiency [12]. Using only one active switch, a leakage-energy recycling dual DC/DC flyback converter has been introduced [13]. Another single switch topology has been proposed, where the input source and the clamped capacitor are in series in order to transfer energy towards the load through dual voltage multiplier cells. As a result, the converter is able to produce a very high voltage while having a high conversion efficiency [14]. A reduced-size, two-switch converter was proposed with a non-isolated high voltage gain, which results in a very simple circuit with continuous input current and a small ripple [15]. A parallel loaded resonant converter providing a wide output voltage range was introduced in [16]. By modifying the transformer turns ratio, it can become applicable in high power environments. A two channel converter family was proposed, where the energy was able to flow from the input to the output within the channels, and also among the two channels. These converters were analyzed in both symmetrical and asymmetrical conditions [17], [18].

This paper proposes a new approach to control the power flow of the four channel buck converter introduced in [19]. Based on experience, the conventional duty ratio based control of this converter faces difficulties since changing the duty ratio of a single switch affects the power flow in multiple channels simultaneously. On the other hand, the newly proposed method enables the direct control of each channel’s power flow without any unwanted consequences for the rest of channels. In this paper, general cases of asymmetrical input voltages and output loads are assumed, and the aim is to produce predefined output voltages. This requires overall control of the power exchange among the converter channels. Efficient control strategies are presented for various use-cases. The presented method can be beneficially applied when using a converter to feed five level voltage source inverter (VSI) systems, which facilitates the reduction of their harmonic distortion.

The outline of the paper is as follows. Section II briefly summarizes the operation of a converter, which is crucial to understanding the control strategies. Section III derives a steady state analysis of the converter with energy equations for the discontinuous current conduction mode (DCM). Section IV presents a design method for power flow control. Section V concentrates on the proposed control in partially asymmetrical cases. Control characteristics are presented in Section VI. Section VII shows the simulation and experimental results. Finally, some conclusions are presented in Section VIII.



Ⅱ. BASIC OPERATION OF THE CONVERTER

A circuit diagram of a four-channel buck converter can be seen in Fig. 1. The operation of the converter is briefly summarized in this paper. Further information can be found in [19]. During the investigation of the lossless components, ripple free input and output voltages are presumed, and the commutation intervals are neglected among the switches. In the analytical study, one switching cycle is examined, which is built up from three time intervals (0p, 1p, 2p). Ts is the switching period, and 그림입니다.
원본 그림의 이름: CLP0000135c035c.bmp
원본 그림의 크기: 가로 221pixel, 세로 114pixel is the resonant angular frequency. Steady-state operating waveforms of the converter in the DCM are shown in Fig. 2. They include the resonant currents iLp and iLn of both inductors and the resonant voltage of the switched capacitor vc.


그림입니다.
원본 그림의 이름: CLP0000135c0001.bmp
원본 그림의 크기: 가로 1242pixel, 세로 847pixel

Fig. 1. Four-channel buck converter.


그림입니다.
원본 그림의 이름: CLP0000135c0002.bmp
원본 그림의 크기: 가로 635pixel, 세로 983pixel

Fig. 2. Time function of the capacitor voltage and inductor current.


Interval 0p [0 < ωt < αp] (see the red continuous line in Fig. 3). Here, the controlled switch Sp is turned on in order to charge the switched capacitor C and to energize the inductor L in the positive (p) channel. The switches Scp1 and Scp2 are turned off. The voltage of the capacitor vc sinusoidally increases, while the sinusoidal current flows through the circuit Vip-Sp-L-Dcp-Vop1-Vop2-C. The instantaneous value of the inductor current at the end of this interval is icp)=iLpp)=ILpa.


그림입니다.
원본 그림의 이름: CLP0000135c0003.bmp
원본 그림의 크기: 가로 1242pixel, 세로 846pixel

Fig. 3. Current paths during switching intervals.


Interval 1p [αp < ωt < αcp] (see the blue continuous line in Fig. 3). At the beginning of this interval, the controlled switch Sp is turned off, while Scp1 is turned on using the energy of L to feed the output. Vc remains constant in this interval, while the current flows in the circuit L-Dcp-Vop1-Scp1. As a result, iLp linearly decreases, and at the end of this interval iLpcp)=ILpb.

Interval 2p [αcp < ωt < αep] (see the green continuous line in Fig. 3). Both Sp and Scp1 are turned off, and Scp2 is turned on. When the current is flowing in the circuit L- Scp2-Vop2-Dp, all of the energy of the inductor is depleted, and the current iLp becomes zero at the extinction angle αep, that is, iLpep)=ILpc=0. It remains in this state until the end of the period Ts. It is important to note, that this only holds true for the discontinuous conduction mode (DCM). In the continuous conduction mode (CCM), the inductor current cannot reach zero before the beginning of the next period.

Additionally, there is a special operational state of the converter, called the protection mode (see the purple continuous line in Fig. 4 for channel p, and the dashed line for channel n), which is due the voltage of the capacitor reaching the input voltage, Vcp=Vip (or Vcn=-Vin). In this case, the diode Dp (or Dn) turns on making the inductor’s current flow in the circuit L- Dcp- Vop1-Vop2 -Dp. The purpose of this operation mode is to avoid overvoltage of the capacitor and to protect the switches in the circuit in case of a failure.


그림입니다.
원본 그림의 이름: CLP0000135c0004.bmp
원본 그림의 크기: 가로 1229pixel, 세로 843pixel

Fig. 4. Protection mode.


The operation intervals at the negative channel are the same as those written above (see the dashed lines in Fig. 3), only shifted by half a period, 그림입니다.
원본 그림의 이름: CLP0000135c003a.bmp
원본 그림의 크기: 가로 89pixel, 세로 111pixel. The output voltages can be directly controlled by the switching frequency 그림입니다.
원본 그림의 이름: CLP0000135c003b.bmp
원본 그림의 크기: 가로 183pixel, 세로 118pixel or the conduction angles of the controlled switches.

In the paper, positive 그림입니다.
원본 그림의 이름: CLP0000135c003c.bmp
원본 그림의 크기: 가로 295pixel, 세로 107pixel and negative 그림입니다.
원본 그림의 이름: CLP0000135c003d.bmp
원본 그림의 크기: 가로 293pixel, 세로 109pixel sequence symmetrical components are introduced, where xp and xn are the same kind of variables or parameters (e.g. voltages) in channels p and n, respectively. Examples of symmetrical components are as follows: positive sequence input voltage 그림입니다.
원본 그림의 이름: CLP0000135c003e.bmp
원본 그림의 크기: 가로 337pixel, 세로 120pixel and negative sequence input voltage 그림입니다.
원본 그림의 이름: CLP0000135c003f.bmp
원본 그림의 크기: 가로 334pixel, 세로 120pixel. Since Vcn<0, the positive sequence capacitor voltage is 그림입니다.
원본 그림의 이름: CLP0000135c0040.bmp
원본 그림의 크기: 가로 339pixel, 세로 114pixel, and the negative sequence capacitor voltage is 그림입니다.
원본 그림의 이름: CLP0000135c0041.bmp
원본 그림의 크기: 가로 338pixel, 세로 111pixel. Vcp and Vcn are the peak values of the capacitor voltage time function (see Fig. 2).



Ⅲ. ANALYTICAL STUDY BASED ON ENERGY EQUATIONS

In this section, energy pulse equations are analyzed for one switching period, Ts. The equations are mostly derived for channel p, unless those for channel n are crucial for understanding. However, using the equations of channel p, the corresponding channel n equations can easily be produced by the following formal parameter substitutions: xp ↔ xn (except Vcp ↔ -Vcn ), x1 ↔ x1 and x2 ↔ -x2. During the analysis, the following per unit parameters are used: 그림입니다.
원본 그림의 이름: CLP0000135c0042.bmp
원본 그림의 크기: 가로 206pixel, 세로 113pixel, 그림입니다.
원본 그림의 이름: CLP0000135c0043.bmp
원본 그림의 크기: 가로 190pixel, 세로 112pixel, 그림입니다.
원본 그림의 이름: CLP0000135c0044.bmp
원본 그림의 크기: 가로 263pixel, 세로 113pixel, 그림입니다.
원본 그림의 이름: CLP0000135c0045.bmp
원본 그림의 크기: 가로 263pixel, 세로 108pixel, 그림입니다.
원본 그림의 이름: CLP0000135c0046.bmp
원본 그림의 크기: 가로 236pixel, 세로 120pixel, 그림입니다.
원본 그림의 이름: CLP0000135c0047.bmp
원본 그림의 크기: 가로 235pixel, 세로 118pixel, 그림입니다.
원본 그림의 이름: CLP0000135c0048.bmp
원본 그림의 크기: 가로 233pixel, 세로 132pixel, 그림입니다.
원본 그림의 이름: CLP0000135c0049.bmp
원본 그림의 크기: 가로 242pixel, 세로 120pixel, 그림입니다.
원본 그림의 이름: CLP0000135c004a.bmp
원본 그림의 크기: 가로 297pixel, 세로 130pixel, 그림입니다.
원본 그림의 이름: CLP0000135c004b.bmp
원본 그림의 크기: 가로 294pixel, 세로 126pixel, 그림입니다.
원본 그림의 이름: CLP0000135c004c.bmp
원본 그림의 크기: 가로 304pixel, 세로 124pixel and 그림입니다.
원본 그림의 이름: CLP0000135c004d.bmp
원본 그림의 크기: 가로 307pixel, 세로 120pixel, where 그림입니다.
원본 그림의 이름: CLP0000135c004e.bmp
원본 그림의 크기: 가로 279pixel, 세로 118pixel is the resonant frequency, 그림입니다.
원본 그림의 이름: CLP0000135c004f.bmp
원본 그림의 크기: 가로 288pixel, 세로 92pixel is the characteristic impedance and 그림입니다.
원본 그림의 이름: CLP0000135c0050.bmp
원본 그림의 크기: 가로 282pixel, 세로 111pixel is the unit of the current. When Rp1=Rp2, Rp1*=Rp2*=R* and when Vop1=Vop2, Vop1*=Vop2*=Vop1,2*.

The total input energy wip is delivered by the current pulse icp = iLp feeding the converter, while 0 < ωt < αp. The input energy taken from source p can be calculated from the capacitor current and voltage as follows:

그림입니다.
원본 그림의 이름: CLP0000135c0010.bmp
원본 그림의 크기: 가로 1356pixel, 세로 113pixel                  (1)

Similarly:

그림입니다.
원본 그림의 이름: CLP0000135c0011.bmp
원본 그림의 크기: 가로 952pixel, 세로 89pixel                                    (2)

Supposing lossless operation, the total input energy is equal to the total output energy:

그림입니다.
원본 그림의 이름: CLP0000135c0012.bmp
원본 그림의 크기: 가로 879pixel, 세로 84pixel                                       (3)

Assuming the input voltages remain constant, Vc1 is a good candidate for controlling the input energy.

The switched capacitor plays an energy steering role among the input channels p and n.

그림입니다.
원본 그림의 이름: CLP0000135c0013.bmp
원본 그림의 크기: 가로 785pixel, 세로 128pixel                                           (4)

The energy that continues toward the output in channel p (n) and is dissipated on the loads is:

그림입니다.
원본 그림의 이름: CLP0000135c0014.bmp
원본 그림의 크기: 가로 1394pixel, 세로 156pixel                (5)

그림입니다.
원본 그림의 이름: CLP0000135c0015.bmp
원본 그림의 크기: 가로 1406pixel, 세로 131pixel               (6)

The ratio of the energy transferred in channel p, when compared to the total output energy, can be expressed by dividing (5) by (3) as follows:

그림입니다.
원본 그림의 이름: CLP0000135c0016.bmp
원본 그림의 크기: 가로 1505pixel, 세로 250pixel           (7)

similarly:

그림입니다.
원본 그림의 이름: CLP0000135c0017.bmp
원본 그림의 크기: 가로 1510pixel, 세로 244pixel           (8)

This shows that Vc2 is a good candidate for controlling the energy exchange among the input channels p and n.

In the DCM, the output energy pulses in channels p1 and p2 for the above described intervals, which can be calculated as follows:

0 < ωt < αp

그림입니다.
원본 그림의 이름: CLP0000135c0018.bmp
원본 그림의 크기: 가로 1022pixel, 세로 112pixel                                 (9)

그림입니다.
원본 그림의 이름: CLP0000135c0019.bmp
원본 그림의 크기: 가로 1028pixel, 세로 113pixel                                  (10)

αp < ωt < αcp

그림입니다.
원본 그림의 이름: CLP0000135c001a.bmp
원본 그림의 크기: 가로 1050pixel, 세로 114pixel                                 (11)

그림입니다.
원본 그림의 이름: CLP0000135c001b.bmp
원본 그림의 크기: 가로 271pixel, 세로 108pixel                                                                   (12)

αcp < ωt < αep

그림입니다.
원본 그림의 이름: CLP0000135c001c.bmp
원본 그림의 크기: 가로 273pixel, 세로 103pixel                                                                   (13)

그림입니다.
원본 그림의 이름: CLP0000135c001d.bmp
원본 그림의 크기: 가로 626pixel, 세로 116pixel                                                   (14)

By adding equations (9), (11) and (13) and (10), (12) and (14), the energy transferred through channels p1 and p2 and dissipated on the loads can be calculated for one switching period.

그림입니다.
원본 그림의 이름: CLP0000135c001e.bmp
원본 그림의 크기: 가로 1198pixel, 세로 147pixel                          (15)

그림입니다.
원본 그림의 이름: CLP0000135c001f.bmp
원본 그림의 크기: 가로 984pixel, 세로 140pixel                                    (16)

The total output energy of channel p can be calculated by adding equations (15) and (16). This is equal to the energy (wop) supplied to channel p after deducting the capacitor’s energy change [see (5)]:

그림입니다.
원본 그림의 이름: CLP0000135c0020.bmp
원본 그림의 크기: 가로 1432pixel, 세로 108pixel               (17)

From (17),  can be expressed as:

그림입니다.
원본 그림의 이름: CLP0000135c0021.bmp
원본 그림의 크기: 가로 1012pixel, 세로 110pixel                                  (18)

Substituting (18) into (15), the following equation can be expressed for the output energy wop1:

그림입니다.
원본 그림의 이름: CLP0000135c0022.bmp
원본 그림의 크기: 가로 1332pixel, 세로 151pixel                    (19)

Equations (16) and (19) indicate that ILpb is a good candidate to control the energy exchange among output channels p1 and p2. Similarly, ILnb is a good candidate among channels n1 and n2.

Vop2 can be expressed from (16) as follows:

그림입니다.
원본 그림의 이름: CLP0000135c0023.bmp
원본 그림의 크기: 가로 1102pixel, 세로 255pixel                              (20)

Substituting (20) into (19), Vop1 can be calculated as follows:

그림입니다.
원본 그림의 이름: CLP0000135c0024.bmp
원본 그림의 크기: 가로 1088pixel, 세로 158pixel                               (21)

where:

그림입니다.
원본 그림의 이름: CLP0000135c0025.bmp
원본 그림의 크기: 가로 1362pixel, 세로 259pixel                   (22)

Instead of energy pulses, average powers are used exclusively from now on, which can be directly calculated by multiplying the energy pulse values with the switching frequency so that: 그림입니다.
원본 그림의 이름: image10.png
원본 그림의 크기: 가로 797pixel, 세로 192pixel.

Based on (20) and (21), it can be concluded that the output voltages (and the powers) are determined by the inductor currents ILpb and ILnb as well as the positive and negative sequence switched capacitor peak voltages, Vc1 and Vc2. Consequently, these four parameters are considered as the control variables (fs is kept constant).

Fig. 5 shows how they influence the power flow of the converter. Based on (3), Vc1 specifies the amount of power fed into the converter. Vc2 determines how this power is shared among input channels p and n (7) and (8). The inductor currents ILpb and ILnb enable the power exchange among output channels p1, p2 and n1, n2, respectively (16) and (19).


그림입니다.
원본 그림의 이름: CLP0000135c0005.bmp
원본 그림의 크기: 가로 1563pixel, 세로 421pixel

Fig. 5. Power flow from the inputs towards the outputs.



Ⅳ. DESIGN CONSIDERATIONS

This section discusses the procedure to design the power flow control. First, the calculation of the control variables Vc1, Vc2, ILpb and ILnb is introduced considering arbitrary steady-state operation points in the DCM. Afterwards, the steps are explained to decide if the operation point is feasible or not. Fig. 6 shows a circuit block diagram to generate the turn on and turn off signals of the controlled switches. The calculated values of the control parameters are denoted as reference values in the figure [Vc1,ref, Vc2,ref, ILpb,ref and ILnb,ref], which are compared to the instantaneous values of the respective variables during the operation [vc(t), iLp(t) and iLn(t)]. Thus, the turn-on and turn-off intervals of the switches are indirectly controlled.


그림입니다.
원본 그림의 이름: CLP0000135c0006.bmp
원본 그림의 크기: 가로 1569pixel, 세로 770pixel

Fig. 6. Generating switching signals.


A. Calculation of Power Flow Control Parameters

The values of L and C determine the resonant frequency. Since the two input currents can only flow in separate intervals, the simultaneous turn-on of the controlled switches Sp and Sn must be avoided. This can be accomplished by choosing the switching frequency so that: 그림입니다.
원본 그림의 이름: CLP0000135c0051.bmp
원본 그림의 크기: 가로 185pixel, 세로 74pixel. On the other hand, an increase of fs is preferred to reduce the output voltage ripple and to avoid degradation of the dynamical performance of the converter. Hence, the switching frequency is chosen as: 그림입니다.
원본 그림의 이름: CLP0000135c0052.bmp
원본 그림의 크기: 가로 408pixel, 세로 116pixel.

For the design, prior knowledge of the following parameters is assumed from the system specifications: Vip, Vin, Vop1, Vop2, Von1, Von2, Rp1, Rp2, Rn1 and Rn2.

The four output powers can be easily calculated by using the well-known equation: 그림입니다.
원본 그림의 이름: CLP0000135c0053.bmp
원본 그림의 크기: 가로 246pixel, 세로 127pixel .

Since lossless circuit components are assumed, the total input energy (average power) is equal to the total output energy (power), wi=wo and Pi=Po. This power is determined by the control variable Vc1, which can be expressed from (3) as follows:

그림입니다.
원본 그림의 이름: CLP0000135c0026.bmp
원본 그림의 크기: 가로 897pixel, 세로 134pixel                                       (23)

The power exchange among the input channels p and n is controlled by the variable Vc2, which can be expressed from (7):

그림입니다.
원본 그림의 이름: CLP0000135c0027.bmp
원본 그림의 크기: 가로 820pixel, 세로 148pixel                                           (24)

The control parameter ILpb can be calculated from (16) using (3).

그림입니다.
원본 그림의 이름: CLP0000135c0028.bmp
원본 그림의 크기: 가로 553pixel, 세로 230pixel                                                       (25)

Similarly, ILnb is:

그림입니다.
원본 그림의 이름: CLP0000135c0029.bmp
원본 그림의 크기: 가로 551pixel, 세로 230pixel                                                       (26)


B. Operation Limits

Various operational limits need to be taken into consideration when designing the control. The peak voltages of the capacitor are limited by the available maximum commutation angles 그림입니다.
원본 그림의 이름: image19.png
원본 그림의 크기: 가로 826pixel, 세로 211pixel and 그림입니다.
원본 그림의 이름: image20.png
원본 그림의 크기: 가로 811pixel, 세로 188pixel. In this case, the capacitor current and the choke current waveforms are half sinusoidal. In addition, the instantaneous values of the currents ILpa and ILpb (and similarly ILna and ILnb) are zero (see Fig. 2). By substituting ILpa = ILpb =0 into (15) and (16) (and similarly ILna = ILnb =0 into the n channel equivalent equations), the capacitor voltage Vc1 is limited as follows:

그림입니다.
원본 그림의 이름: CLP0000135c002a.bmp
원본 그림의 크기: 가로 1274pixel, 세로 148pixel                       (27)

By substituting ILpa=0 into (18) (and similarly ILna = 0 into the n channel equivalent equation), the limitations of Vc2 can be obtained as follows:

그림입니다.
원본 그림의 이름: CLP0000135c002b.bmp
원본 그림의 크기: 가로 1263pixel, 세로 82pixel                       (28)

The inductor currents ILpb and ILnb have a limit since they cannot be higher than ILpa and ILna (see Fig. 2), respectively. From (18):

그림입니다.
원본 그림의 이름: CLP0000135c002c.bmp
원본 그림의 크기: 가로 1846pixel, 세로 249pixel             &sp;           (29)

그림입니다.
원본 그림의 이름: CLP0000135c002d.bmp
원본 그림의 크기: 가로 1837pixel, 세로 166pixel                         (30)

The converter operates in the protection mode when Vcp=Vip or Vcn=-Vin. To allow for the proper control of the converter, the protection mode has to be avoided. Thus, 그림입니다.
원본 그림의 이름: image25.png
원본 그림의 크기: 가로 693pixel, 세로 210pixel and 그림입니다.
원본 그림의 이름: image26.png
원본 그림의 크기: 가로 811pixel, 세로 186pixel.



Ⅴ. SPECIAL ASYMMETRICAL CASES

To reveal the effects of control variables, the following special asymmetrical cases are examined: asymmetrical output voltages, asymmetrical loads and asymmetrical input voltages. At the same time, only one quantity is considered to be asymmetrical, while the remaining ones are considered to be symmetrical. The relating control characteristics are discussed in Section VI.


A. Asymmetrical Output Voltages

At this point, Vop1≠Vop2. However, Vop1=Von1, Vop2=Von2, Vip=Vin and Rp1=Rp2=Rn1=Rn2. Substituting them into (7) and since Vip=Vi1, it follows that Vc2=0. Substituting the per unit values into (16), ILpb* in the function of Vop2* can be calculated as:

그림입니다.
원본 그림의 이름: CLP0000135c002e.bmp
원본 그림의 크기: 가로 747pixel, 세로 160pixel                                              (31)

Substituting the per unit values into (21), ILpb* can also be calculated in the function of Vop1* as:

그림입니다.
원본 그림의 이름: CLP0000135c002f.bmp
원본 그림의 크기: 가로 578pixel, 세로 223pixel                                                      (32)

where: 

그림입니다.
원본 그림의 이름: CLP0000135c0030.bmp
원본 그림의 크기: 가로 557pixel, 세로 137pixel                                                      (33)

그림입니다.
원본 그림의 이름: CLP0000135c0031.bmp
원본 그림의 크기: 가로 1407pixel, 세로 136pixel                 (34)

where:

그림입니다.
원본 그림의 이름: CLP0000135c0032.bmp
원본 그림의 크기: 가로 442pixel, 세로 90pixel                                                            (35)


B. Asymmetrical Loads

At this point, the case where Rp1≠Rp2, but Rp1=Rn1, Rp2=Rn2, Vip=Vin=Vi1 and Vop1=Vop2=Von1=Von2 is investigated. Based on (7) Vc2=0.

Substituting the per unit values into (16), ILpb* in function of Rp2* can be calculated as:

그림입니다.
원본 그림의 이름: CLP0000135c0033.bmp
원본 그림의 크기: 가로 816pixel, 세로 226pixel                                           (36)

Similarly, ILpb* as a function of Rp1* can be expressed from (21) as:

그림입니다.
원본 그림의 이름: CLP0000135c0034.bmp
원본 그림의 크기: 가로 978pixel, 세로 225pixel                                    (37)


C. Asymmetrical Input Voltages

In this case, Vip≠Vin, Vop1=Vop2=Von1=Von2, Rp1=Rp2=Rn1= Rn2 and all of the output powers are identical. At this point, 그림입니다.
원본 그림의 이름: CLP0000135c0054.bmp
원본 그림의 크기: 가로 199pixel, 세로 121pixel is based on (7) and:

그림입니다.
원본 그림의 이름: CLP0000135c0035.bmp
원본 그림의 크기: 가로 202pixel, 세로 71pixel                                                                       (38)

This shows that the asymmetry in the input voltages can be efficiently compensated by Vc2.

The output power (and voltage) can be controlled by Vc1 [see (23)]:

그림입니다.
원본 그림의 이름: CLP0000135c0036.bmp
원본 그림의 크기: 가로 630pixel, 세로 140pixel                                                   (39)

ILpb and ILnb are determined by (25) and (26). As long as Vi1 remains constant, no adjustment is required at these control variables. If Vi1 changes, ILpb and ILnb need to be adjusted accordingly.


D. Symmetrical Operation Points

As a special case, symmetrical operation points can also be realized, by considering that all of the circuit and control parameters are identical in the p and n sides. Vc1 can be expressed using (23):

그림입니다.
원본 그림의 이름: CLP0000135c0037.bmp
원본 그림의 크기: 가로 497pixel, 세로 143pixel                                                         (40)

In symmetrical operation, all of the negative sequence components are zero. As a result, Vc2 is also zero. By subtracting (19) from (16), the control parameter ILpb* can be calculated as follows:

그림입니다.
원본 그림의 이름: CLP0000135c0038.bmp
원본 그림의 크기: 가로 853pixel, 세로 162pixel                                         (41)

The ratio of the currents ILpb* and ILpa* can also be calculated. Squaring (41), dividing it by (18) and substituting the per unit values yields:

그림입니다.
원본 그림의 이름: CLP0000135c0039.bmp
원본 그림의 크기: 가로 754pixel, 세로 181pixel                                              (42)

As expected, this ratio gives 0.5 since half of the energy is delivered to the output p1 and half to p2. The situation is also the same in channel n.



Ⅵ. ASYMMETRICAL CONTROL CHARACTERISTICS

This section is concerned with the relationships among the output voltages, input voltages and control variables. As the steady state analysis pointed out, during asymmetrical conditions, the capacitor peak voltages Vc1* and Vc2* and the inductor currents ILpb* and ILnb* are appropriate parameters to control the output voltages and powers. Various scenarios are examined, including changes of the loads and the input voltages of the system. The characteristic curves were calculated in MATLAB R2018b. Numerous operation points were selected and marked with capital letters A-I, and simulations and laboratory measurements were carried (see Table I). In the characteristics, the green curves indicate symmetrical operation, while the black curves represent the protection mode and further operational limits. The continuous lines mark the channel p (or p1) parameters, while the dashed lines represent the channel n (or p2) parameters.


TABLE I SELECTED OPERATION POINTS FOR ASYMMETRICAL OPERATION, DCM, WHERE FS*=1

 

Rp1*[pu]

Rp2*[pu]

Vip*[pu]

Vin*[pu]

Vc1*[pu]

Vc2*[pu]

ILpb*[pu]

ILnb*[pu]

A

asym load

6.0

3

1.00

1.00

0.10

0.00

0.40

0.40

B

asym load

1.5

3

1.00

1.00

0.20

0.00

0.26

0.26

C

asym outp. voltage

1.5

1.5

1.00

1.00

0.47

0.00

0.78

0.78

D, prot

asym outp. voltage

0.8

0.8

1.00

1.00

1.00

0.00

0.52

0.52

E

asym input

1.5

1.5

0.40

1.60

0.26

-0.60

0.51

0.51

F

asym input

1.5

1.5

1.30

0.67

0.26

0.33

0.51

0.51

G

sym

1.5

1.5

1.00

1.00

0.26

0.00

0.52

0.52

H

fully asym

0.6

0.8

0.86

1.14

0.30

-0.10

0.63

0.63


A. Change of the Output Voltage

Fig. 7 shows the effects of output voltage changes during constant and symmetrical loads and input voltages in the control plain set-up by Vc1 and ILpb. The point G represents a symmetrical operation point. Moving from G to C, Vop1* remains constant, while Vop2* increases by a factor of 1.6 when compared to its value at point G. By increasing both of the control variables, a new stable operation point is reached. Fig. 8 represents one of the advantages of the proposed control method. Vc1*=1 is reached during operation that gives immediate information that protection mode is reached and Vc1* cannot be increased any further as shown in point D. This also means that the total transferred power cannot be elevated any more.


그림입니다.
원본 그림의 이름: CLP0000135c0007.bmp
원본 그림의 크기: 가로 1235pixel, 세로 956pixel

Fig. 7. Control characteristics Vop1,2*(Vc1*,ILpb*),R*=1.5.


그림입니다.
원본 그림의 이름: CLP0000135c0008.bmp
원본 그림의 크기: 가로 1239pixel, 세로 963pixel

Fig. 8. Control characteristics Vop1,2*(Vc1*,ILpb*),R*=0.8.


B. Change of the Load

Fig. 9 represents the effects of load changes at a constant output voltage and input voltage. Assuming starting from the symmetrical operation point G, one of the load resistances, e.g. Rp2* increases from 1.5 to 3. Although the operation becomes asymmetrical, by lowering the values of the control variables to 그림입니다.
원본 그림의 이름: CLP0000135c0055.bmp
원본 그림의 크기: 가로 242pixel, 세로 66pixel and 그림입니다.
원본 그림의 이름: CLP0000135c0056.bmp
원본 그림의 크기: 가로 296pixel, 세로 75pixel, the same output voltage 그림입니다.
원본 그림의 이름: CLP0000135c0057.bmp
원본 그림의 크기: 가로 343pixel, 세로 78pixel can be maintained (B) like the original one. Here, due to the elevated resistance Rp2* (note that Vop1,2* is kept constant), the total output power is decreased, which was achieved by lowering Vc1. On the other hand, the ratio of the power balance 그림입니다.
원본 그림의 이름: CLP0000135c0058.bmp
원본 그림의 크기: 가로 115pixel, 세로 133pixel is increased, which was achieved by lowering ILpb (see Fig. 5). At operation point A, the current of the inductor is close to the limitation.


그림입니다.
원본 그림의 이름: CLP0000135c0009.bmp
원본 그림의 크기: 가로 1225pixel, 세로 955pixel

Fig. 9. Control characteristics Rp1,2*(Vc1*,iLpb*),Vo *=0.25.


C. Change of the Input Voltage

Fig. 10 shows how changes of the input voltage affect the control characteristics. Here the voltage of the capacitor reaches its maximum (Vc1*max) before the protection mode. From the symmetrical operation mode G, if the voltage Vip* gets higher (or Vin* lower), a stable operation point (F) with symmetrical output voltages (Vop1,2=Von1,2) can be ensured by keeping Vc1*=const.


그림입니다.
원본 그림의 이름: CLP0000135c000a.bmp
원본 그림의 크기: 가로 1208pixel, 세로 961pixel

Fig. 10. Control characteristics Vip,n*(Vc1*,Vc2*),Vo*=0.25,R*=1.5.


On the other hand, if Vip* gets smaller (or Vin* gets larger), when Vc1*=const., symmetrical output voltages can be accomplished with 그림입니다.
원본 그림의 이름: CLP0000135c0059.bmp
원본 그림의 크기: 가로 362pixel, 세로 72pixel (operation point E). Vc2 controls the power flow among the input channels p and n.



Ⅶ. SIMULATION AND EXPERIMENTAL VERIFICATION

The considerations and analyses introduced above were tested in both simulation and laboratory environments.

The simulation was run in MATLAB Simulink 2018Rb. A 100W prototype of the converter was built with the following circuit parameters: C=1 µF, Ci=10 µF, Co=200 µF and L=10 µH. Here, the resonant frequency is fr=50.329 kHz. The input voltage range of the converter is 1-24V for both the p and n channels, the output voltage range of the converter is also the same. IRF530NPB MOSFETs and STTH802 diodes were used, while the open loop control was realized by a TMS320F283790 DSP. The asymmetrical operation of the converter was tested under numerous control parameter combinations considering changes of the load, input voltage and output voltage. The input voltage was chosen to be Vip=Vin=20V, except at operation points E (Vip=5V, Vin=20V) and F (Vip=20V, Vin=10V). A comparison of the theoretical, simulation and experimental results can be seen in Table II. Figs. 11-15 show steady-state waveforms of the capacitor voltage vc(t), inductor currents iLp(t) and iLn(t), and capacitor current ic(t). The red waveforms represent experimental results, while the blue ones show simulation outcomes. Fig. 11 shows the time functions at operation point A when the load is asymmetrical. Fig. 12. presents the effects of asymmetrical output voltages at operation point C. Fig. 13 represents operation point D, which is at the border of the protection mode. Consequently, the capacitor peak voltage just reaches the input voltage level. Fig. 14 demonstrates operation point E, where the input voltages are asymmetrical.


TABLE II COMPARISON OF THEORETICAL, SIMULATION AND EXPERIMENTAL RESULTS

 

ILpb [A]

 

 

ILnb[A]

 

 

Vcp[V]

 

 

Vcn[V]

 

 

Vop1[V]

 

 

Vop2[V]

 

 

 

Calc.

Sim.

Lab.

Calc.

Sim.

Lab.

Calc.

Sim.

Lab.

Calc.

Sim.

Lab.

Calc.

Sim.

Lab.

Calc.

Sim.

Lab.

A

2.55

2.55

2.52

2.55

2.55

2.47

1.97

1.98

2.35

-1.98

-1.98

-2.22

5.03

5.08

5.00

4.99

5.00

4.99

B

1.61

1.61

1.45

1.61

1.61

1.52

3.93

3.95

4.12

-3.93

-3.95

-4.30

4.98

4.99

4.90

5.00

5.01

4.90

C

4.91

4.91

5.10

4.91

4.91

4.08

9.38

9.40

8.88

-9.38

-9.40

-9.62

4.98

5.01

4.80

8.00

7.99

7.70

D

3.26

3.19

3.35

3.26

3.19

3.30

20.36

20.10

19.63

-20.36

-20.10

-20.50

8.00

7.93

6.70

6.20

6.15

4.70

E

2.02

2.02

1.95

2.02

2.02

1.98

-4.21

-4.20

-4.25

-10.79

-10.80

-11.25

3.14

3.15

2.90

3.13

3.13

2.80

F

2.43

2.43

2.40

2.43

2.43

2.38

8.95

8.97

9.31

1.05

1.04

1.00

3.76

3.78

3.50

3.76

3.76

3.50

G

3.26

3.25

2.80

3.26

3.26

2.78

5.28

5.30

5.38

-5.28

-5.30

-5.38

4.99

5.01

4.80

5.01

5.00

4.80

H

3.46

3.47

3.45

3.47

3.48

3.25

3.58

3.60

4.13

-7.12

-7.13

-8.13

2.80

2.81

2.67

3.50

3.50

3.70


그림입니다.
원본 그림의 이름: CLP0000135c000b.bmp
원본 그림의 크기: 가로 1264pixel, 세로 968pixel

Fig. 11. Time functions at operation point A, where the time unit is 2µsec/Div (blue: simulated; red: measured).


그림입니다.
원본 그림의 이름: CLP0000135c000c.bmp
원본 그림의 크기: 가로 1332pixel, 세로 970pixel

Fig. 12. Time functions at operation point C, where the time unit is 1µsec/Div (blue: simulated; red: measured).


그림입니다.
원본 그림의 이름: CLP0000135c000d.bmp
원본 그림의 크기: 가로 1335pixel, 세로 971pixel

Fig. 13. Time functions at operation point D, where the time unit is 2µsec/Div (blue: simulated; red: measured).


그림입니다.
원본 그림의 이름: CLP0000135c000e.bmp
원본 그림의 크기: 가로 1338pixel, 세로 964pixel

Fig. 14. Time functions at operation point E, where the time unit is 2µsec/Div (blue: simulated; red: measured).


그림입니다.
원본 그림의 이름: CLP0000135c000f.bmp
원본 그림의 크기: 가로 1337pixel, 세로 937pixel

Fig. 15. Time functions at operation point H, where the time unit is 2µsec/Div (blue: simulated; red: measured).


Consequently, 그림입니다.
원본 그림의 이름: CLP0000135c005a.bmp
원본 그림의 크기: 가로 208pixel, 세로 72pixel, which means that 그림입니다.
원본 그림의 이름: CLP0000135c005b.bmp
원본 그림의 크기: 가로 308pixel, 세로 83pixel. Fig. 15 illustrates fully asymmetrical operation at point H.

The compared theoretical and simulation results are practically the same. In addition, laboratory tests are also in good agreement. Small deviations of the latter were due to voltage drops of the real diodes, non-ideal circuit elements and non-linear behavior of the semiconductor switches and passive components.



Ⅷ. CONCLUSION

A new power flow control has been proposed for a four channel resonant buck converter, while operated in the zero current switching (ZCS) mode. Control of the output voltages and powers were achieved through control variables such as the inductor currents and the peak voltage levels of the capacitor. The switching frequency was fixed at its maximal value, which was determined by the resonant frequency. The new control strategy provides an excellent opportunity to control the total transferred power (by Vc1), the exchange of power among the input channels p and n (by Vc2) and the power exchange among the output channels p1 and p2 [n1 and n2] (by ILpb [ILnb]). Numerous operation points have been examined in order to verify the theory of the power flow control. Both tests and simulation results have been presented to confirm and verify the theoretical considerations.



ACKNOWLEDGMENT

Project no. FIEK_16-1-2016-0007 has been implemented with the support provided from the National Research, Development and Innovation Fund of Hungary, financed under the Centre for Higher Education and Industrial Cooperation - Research infrastructure development (FIEK_ 16) funding scheme. The research reported in this paper has also been supported by the National Research, Development and Innovation Fund (TUDFO/51757/2019-ITM, Thematic Excellence Program).



REFERENCES

[1] W. Sun, X. Jin, L. Zhang, H. Hu, and Y. Xing, “Analysis and design of a multi-resonant converter with a wide output voltage range for EV charger applications,” J. Power Electron., Vol. 17, No. 4, pp. 849-859, Jul. 2017.

[2] N. Hassan, Y.-J. Kim, B.-M. Han, and J.-Y. Lee, “A hybrid DC/DC converter for EV OBCs using full-bridge and resonant converters with a single transformer,” J. Power Electron., Vol. 17, No. 4, pp. 849-859, Jul. 2017.

[3] H.-N. Vu and W. Choi, “A novel dual full-bridge LLC resonant converter for CC and CV charges of batteries for electric vehicles,” IEEE Trans. Ind. Electron., Vol. 65, No. 3, pp. 2212-2225, Mar. 2018.

[4] H. Bi, P. Wang, and Y. Che, “Structural boost three-level DC-DC converter with wide voltage-gain range for fuel cell applications,” J. Power Electron., Vol. 18, No. 5, pp. 1303-1314, Sep. 2018.

[5] T. Ahmadi, M. Hamzeh, and E. Rokrok, “Hierarchical control scheme for three-port multidirectional DC-DC converters in bipolar DC microgrids,” J. Power Electron., Vol. 18, No. 5, pp. 1595-1607, Sep. 2018.

[6] B. Xie, J. Wang, Y. Jin, Y. Ji, and C. Ma, “Power distribution control scheme for a three-phase interleaved DC/DC converter in the charging and discharging processes of a battery energy storage system,” J. Power Electron., Vol. 18, No. 4, pp. 1211-1222, Jul. 2018.

[7] S. Cetin, “High efficiency design procedure of a second stage phase shifted full bridge converter for battery charge applications based on wide output voltage and load ranges,” J. Power Electron., Vol. 18, No. 4, pp. 975-984, Jul. 2018.

[8] Y. Wang, L. Yang, G. Li, and S. Tu, “A parameter selection method for multi-element resonant converters with a resonant zero point,” J. Power Electron., Vol. 18, No. 2, pp. 332-342, Mar. 2018.

[9] Z.-Y. Chen and Y. Chen, “A secondary resonance soft switching half bridge DC-DC converter with an inductive output filter,” J. Power Electron., Vol. 17, No. 6, pp. 1391-1401, Nov. 2017.

[10] M.-K. Nguyen, T.-D. Duong, Y.-C. Lim, and J.-H. Choi, “Active CDS-clamped L-type current-fed isolated DC-DC converter,” J. Power Electron., Vol. 18, No. 4, pp. 955-964, Jul. 2018.

[11] M. Yaqoob, K.-H. Loo, and Y. M. Lai, “Fully soft-switched dual-active-bridge series-resonant converter with switched- impedance-based power control,” IEEE Trans. Power Electron., Vol. 33, No.11, pp. 9267-9281, Nov. 2018.

[12] H. M. Suryawanshi, S. Pachpor, T. Ajmal, G. G. Talapur, S. Sathyan, M. S. Ballal, V. B. Borghate, and M. R. Ramteke, “Hybrid control of high-efficient resonant converter for renewable energy system,” IEEE Trans. Ind. Informat., Vol. 14, No. 5, pp. 1835-1845, May 2018.

[13] L.-S. Yang, “Novel dual DC-DC flyback converter with leakage-energy recycling,” J. Power Electron., Vol. 18, No.4, pp. 1007-1014, Jul. 2018.

[14] X. Hu, B. Gao, Y. Huang, and H. Chen, “Novel single switch DC-DC converter for high step-up conversion ratio,” J. Power Electron., Vol. 18, No. 3, pp. 662-671, May 2018.

[15] M.-K. Nguyen, Y.-O. Choi, G.-B. Cho, and Y.-C. Lim, “Two-switch non-isolated step-up DC-DC converter,” J. Power Electron., Vol. 18, No. 3, pp. 651-661, May 2018.

[16] M. Kim, H. Jeong, B. Han, and S. Choi, “New parallel loaded resonant converter with wide output voltage range,” IEEE Trans. Power Electron., Vol. 33, No. 4, pp. 3106- 3114, Apr. 2018.

[17] J. Hamar and I. Nagy, “Control features of dual-channel DC-DC converters,” IEEE Trans. Ind. Electron., Vol. 49, No. 6, pp. 1293-1305, Dec. 2002.

[18] J. Hamar and I. Nagy, “Asymmetrical operation of dual channel resonant DC-DC converters,” IEEE Trans. Power Electron., Vol. 18, No. 1, pp. 83-94, Jan. 2003.

[19] L. Litvani and J. Hamar, “New five level resonant DC/DC buck converter,” in Proceeding of IEEE Power Electronics and Motion Control Conference (IEEE-PEMC), pp. 1006- 1011, 2018.



그림입니다.
원본 그림의 이름: image56.jpeg
원본 그림의 크기: 가로 183pixel, 세로 204pixel

Lilla Litvani received her M.S. degree in Electrical Engineering from the Budapest University of Technology and Economics, (BME), Budapest, Hungary, in 2015, where she is presently working towards her Ph.D. degree in the Department of Automation and Applied Informatics. Her current research interests include the modelling, analysis, control and optimization of power converters and DC microgrids.


그림입니다.
원본 그림의 이름: image57.jpeg
원본 그림의 크기: 가로 164pixel, 세로 194pixel

Janos Hamar received his M.S. and Ph.D. degrees from the Budapest University of Technology and Economics, Budapest, Hungary, in 1998 and 2002, respectively. He was a Research Fellow at the Hungarian Academy of Sciences, Budapest, Hungary, from 1998 to 2001. Later, he worked as a Development Engineer for Exendis Industrie Automation GmbH, Freiburg, Germany. From 2004 to 2006, he was a Research Fellow at Utsunomiya University, Utsunomiya, Japan. He is presently working as an Associate Professor at the Budapest University of Technology and Economics. His current research interests include the modelling, analysis, control and optimization of power converters.