https://doi.org/10.6113/JPE.2019.19.6.1413
ISSN(Print): 1598-2092 / ISSN(Online): 2093-4718
Zero-Voltage and Zero-Current Switching Interleaved Two-Switch Forward Converter
Enhui Chu†, Jianqun Bao*, Qi Song*, Yang Zhang*, Haolin Xie*, Zhifang Chen*, and Yue Zhou*
†,*College of Information Science and Engineering, Northeast University, Liaoning, China
Abstract
In this paper, a novel zero-voltage and zero-current switching (ZVZCS) interleaved two switch forward converter is proposed. By using a coupled-inductor-type smoothing filter, a snubber capacitor, the parallel capacitance of the leading switches and the transformer parasitic inductance, the proposed converter can realize soft-switching for the main power switches. This converter can effectively reduce the primary circulating current loss by using the coupled inductor and the snubber capacitor. Furthermore, this converter can reduce the reverse recovery loss, parasitic ringing and transient voltage stress in the secondary rectifier diodes caused by the leakage inductors of the transformer and the coupled inductance. The operation principle and steady state characteristics of the converter are analyzed according to the equivalent circuits in different operation modes. The practical effectiveness of the proposed converter was is illustrated by simulation and experimental results via a 500W, 100 kHz prototype using the power MOSFET.
Key words: Interleaved, Passive auxiliary resonant circuit, Two switch forward converter, Zero-current-switching (ZCS), Zero-voltage-switching (ZVS)
Manuscript received Mar. 2, 2019; accepted Jun. 27, 2019
Recommended for publication by Associate Editor Chun-An Cheng.
†Corresponding Author: chuenhui@mail.neu.edu.cn Tel: +86-24-8368-9605, Fax: +86-24-8368-9605, Northeast University
*College of Inform. Science and Eng., Northeast University, China
Ⅰ. INTRODUCTION
With the development of power electronics technology, soft switching technology plays an important role in high frequency processes of PWM converters. Under the same condition, the soft switching converters can work at higher switching frequency compared to the hard switching converters. Meanwhile, soft switching technology can improve the operating reliability of switches, reduce the sizes of converters, suppress excessive di/dt and dv/dt, reduce power losses and enhance efficiency. Moreover, it can effectively cut down electromagnetic interference (EMI) and system noise [1], [2].
The forward converter is a widely used isolated DC/DC converter, especially in low and medium power applications [3]-[10]. Since the requirements of topological standardization in system integration are higher and higher, a series of forward converters has been presented. Two-switch forward converters [11]-[19] reduce the voltage stress on switches and creates development conditions for high-input-voltage forward converters. The active clamp forward converters [14]-[18] solve the problem of high turn-off voltage spikes at the switches of forward converters. However, these two types of converters both increase the number of switches without increasing the transmission power. Although the active clamp circuit can create the ZVS turn-on condition for the main and auxiliary switches, the efficiency of the converter is restricted as a result of increasing the resonant circuit losses and circulating losses. Interleaved two-switch forward converters [20]-[24] reduce the output filter current ripple and the filter elements size. Moreover, they improve the power density and the fault tolerance of the converter. However, the interleaved structure cannot solve the problem of high turn-off voltage spikes at the switches.
Paper [25] proposed an interleaved two-switch forward converter with a coupled inductance. By employing a coupled output inductor, parallel capacitor of the switch and transformer leakage inductors, the converter in [25] can realize soft switching for all of the switches, reduce the circulating current, and achieve high efficiency. However, in order to rapidly decrease the primary current to zero, it has to increase the turn-ratio of the coupled inductor. In this case, the voltage stress and parasitic ringing in the freewheeling and rectification diodes are increased. For the purpose of suppressing the parasitic ringing, the saturable reactors connected in series with the secondary windings are essential [26]. However, the use of the saturable reactors produces an additional loss and heat in the saturable core.
Accordingly, based on the converter proposed in [25], aiming at the DC converters used in aviation secondary power supplies, this paper proposed a novel interleaved two-switch forward converter that employs a coupled inductor and a snubber capacitance. The proposed converter has the following advantages. ① By using a simple auxiliary circuit, the proposed converter can realize soft-switching for all of the power switches. In addition, this topology improves the reset speed of the primary current. Therefore, the circulating current loss is further reduced. ② By increasing the ratio of the coupled inductor, the ZCS control of the lagging switches can be more easily realized. In addition, the proposed converter can effectively reduce the reverse recovery loss, the parasitic ringing and voltage stress in the secondary rectification diodes. ③ The circulating current of the auxiliary circuit can be self-adjusted according to the load, which is helpful for improving efficiency under a light load. Consequently, the converter can maintain a high efficiency over a wide load range.
Ⅱ. CIRCUIT TOPOLOGY AND OPERATION PRINCIPLE
A. Circuit Topology
Fig. 1 shows the topology structure of the proposed ZVZCS ITSF converter with a coupled inductance and a snubber capacitor. E is the input dc voltage source. The switches S1 and S4, the transformer T2, the diodes D2 and D4 and the rectifier diode D6 constitute one of the forward converters. The switches S2 and S3, the transformer T1, the diodes D1 and D3 and the rectifier diode D5 constitute the other forward converter. The passive snubber capacitors C1 (C2) parallel with S1 (S2). Ls1 (Ls2) is the secondary equivalent leakage inductance of the transformer T1 (T2). Lm1 (Lm2) is the magnetizing inductance of the transformer T1 (T2). Ld1 and Ld2 compose the coupled output inductor. The secondary auxiliary circuit consists of the snubber capacitor Cs, the auxiliary diodes Ds1 and Ds2, the freewheeling diode Df and the coupled output inductor. Co is the output filter capacitor. Ro is the load.
Fig. 1. Proposed ZVZCS ITSF converter.
B. Operation Principle
Working waveforms and operation stages of the proposed converter are illustrated in Fig. 2 and Fig. 3, respectively. As shown in Fig. 2, vg1~vg4 are driving waveforms of S1~S4, respectively. Moreover, S1 (S4) and S2 (S3) are driven complementary with a dead-time td. S4 (S3) turns off after S1 (S2) with a delay-time tδ. Ts is one switching period. ton is the conduction time of the switches. The converter output duty ratio is D=(ton-tδ)/Th, where Th = Ts/2.
Fig. 2. Working waveforms of the proposed converter.
|
(a) |
|
(b) |
|
(c) |
|
(d) |
|
(e) |
|
(f) |
|
(g) |
|
(h) |
|
(i) |
|
(j) |
In order to simplify the analysis, several assumptions are made as follows.
(1) All of the switches, diodes, capacitors and inductors are ideal devices.
(2) The passive snubber capacitors in parallel with the switches are expressed as C1=C2=C.
(3) Np and Ns are the turns of the transformer primary and secondary, respectively. In addition, the transformer turn ratio is NT=Np/Ns. The roll line resistance of the transformer is neglected.
(4) The magnetizing inductances are expressed as Lm1= Lm2=Lm, which are large enough to keep the magnetizing current constant during the charging or discharging periods of C1 or C2.
(5) The coupled output inductors Ld1 and Ld2 are tightly coupled with each other. n1 and n2 are the turns of the coupled output inductors Ld1 and Ld2, respectively. In addition, the coupled inductor turn ratio is m=n2/n1. Furthermore, Ld1 is large enough and the current through Ld1 is continuous.
(6) The output capacitor Co is large enough to be considered as a voltage source Vo.
Before t0, referring to Fig. 1, S1, S4 and D6 are in the on state. Meanwhile, S2 and S3 are in the off state, and D1~D5, Ds1, Ds2 and Df are reverse biased. The voltages across C1 and C2 are zero and E, respectively. In addition, the voltage across the snubber capacitor is VCs-max. The dc source transfers energy to the load through the transformer and the rectifier circuit. The magnetizing current iLm2 increases in a linear way. iLm2 satisfies iu=iLm2+iT2, where iT2 is the current through the primary winding of the transformer T2. The ten converter working stages are analyzed as follows.
Stage 1 [t0~t1][see Fig. 3(a)]: At t0, S1 ZVS turns off. In addtion, the energy stored in C2 starts transferring to C1. C1 is charged while C2 is discharged. Ld1 and Lm2 are large enough so that iD6 and iLm2 are considered to be constant during this stage. The voltage across C1 increases linearly as:
(1)The voltage across C2 decreases linearly as:
(2)Where iLm2(t0) is the maximum current value of the magnetizing inductance Lm2. During this stage, both the primary voltage of the transformer T2 and the voltage vd rectified by D6 decrease linearly. vd is expressed as:
(3)The voltage of the coupled inductor Ld2 decreases linearly with a decrease of vd. vLd2 is expressed as:
(4)When vd= VCs-max - vLd2, Ds2 turns on and Stage 1 ends. At t1, the voltage across C1 is expressed as:
(5)Stage 2 [t1~t2][see Fig. 3(b)]: At t1, Ds2 turns on and the load current begins flowing through Ds2. Since Cs is large enough, iLm2 and vCs remain constant during this stage. vd is clamped at (VCs-max+mVo)/(1+m). The voltage vC1 across C1 and the current iD6 through D6 are expressed as:
(6)
(7)Where iLm2(t1)=iLm2(t0), iD6(t1)=iD6(t0).
In order to realize the turn-on condition for Ds2 and to provide a reliable discharge circuit for Cs, it should be ensured that (VCs-max+mVo)/(1+m)＜E/NT.
At t2, vC1 rises to E, vC2 and the transformer primary voltage drop to zero. D2 turns on. Stage 2 ends.
Stage 3 [t2~t3][see Fig. 3(c)]: At t2, D2 turns on, and the voltage across S2 is clamped at zero. The magnetizing current iLm2 continues to be constant. Cs resonates with the transformer secondary leakage inductance Ls, vCs and iCs are expressed as:
(8)
(9)Due to the effect of the snubber capacitance Cs and the transformer secondary leakage inductance Ls, the current iD6 through D6 decreases as:
(10)Where iLm2(t2)=iLm2(t0).
At t3, vCs decreases to zero. Ds2 turns off, and Df turns on, and stage 3 ends. The duration of this stage is expressed as:
(11)Stage 4 [t3~t4][see Fig. 3(d)]: At t3, Ds2 turns off, and Df turns on. The load current starts flowing through Df. The magnetizing current iLm2 continues to be constant. The current iD6 through D6 decrease linearly by the force of vd, and its expression is:
(12)The primary current iu decrease in a linear way as:
(13)Where iLm2(t3)=iLm2(t0).
When iD6 decreases to zero at t4, iu decreases to the magnetizing current iLm. D6 turns off naturally, and stage 4 ends. The duration of this stage is expressed as:
(14)Stage 5 [t4~t5][see Fig. 3(e)]: At t4, D6 turns off. The primary current iu, which is equals to the magnetizing current iLm, flows through S4 and D2 for circulating. At the same time, the load current Io flows through Df, Ld1 and Ld2 for freewheeling. Because iLm is very small, only a few circulating current losses are produced. If S4 turns off during the circulating period, near ZCS turn-off for S4 is achieved due to the existence of the magnetizing current iLm2.
Stage 6 [t5~t6][see Fig. 3(f)]: At t5, S4 turns off, and D4 turns on. The magnetizing current iLm2 feeds back energy to the dc voltage source through D2 and D4. The transformer T2 enters the magnetic reset process. iLm2 decreases linearly as:
(15)Where iLm2(t5)=iLm2(t0).
At t6, S3 turns on, and stage 6 ends. Due to the effect of Ls1, the current through S3 gradually increases from zero, and S3 can achieve ZCS turn-on.
Stage 7 [t6~t7][see Fig. 3(g)]: At t6, S3 and D5 turn on. Df keeps conducting to clamp vd at mVo/(1+m). iLm2 continues to decrease linearly as (15). The current iD5 through D5 and the magnetizing current iLm1 of the transformer T1 increase linearly from zero as (16) and (17), respectively.
(16)
&p; (17)The current iS3 through S3 increases linearly from zero as:
(18)When iu(t)=iLm2(t)-iS3(t)=0, D2 turns off. Due to the effect of D2 and Lm1, S2 achieves ZVZCS turn-on. When the current through D5 increases to the load current Io, Df turns off, and stage 7 ends. The duration of this stage is expressed as:
(19)Stage 8 [t7~t8][see Fig. 3(h)]: At t7, Df turns off. The dc source transfers energy to the load through the transformer T1, D5 and Ld1. Ds1 turns on. The leakage inductance Ls of the transformer and the snubber capacitor Cs begin to resonate. The voltage across Cs increases from zero. vCs and iCs are expressed as:
(20)
(21)At the moment of 1/2 a resonant period, vCs is charged to the maximum value VCs-max. The secondary transient over- voltage is clamped at Vo+VCs-max/(1+m), and iCs decreases to zero. Ds1 softly turns off, and stage 8 ends. VCs-max is expressed as:
(22)The duration of this stage is expressed as:
(23)Stage 9 [t8~t9][see Fig. 3(i)]: At t8, Ds1 turns off. iLm2 continues to decrease as (15). At t9, iLm2 decreases to zero, and D4 turns off. The transformer T2 completes its magnetic reset, and stage 9 ends.
Stage 10 [t9~t10][see Fig. 3(j)]: At t9, D4 turns off. All of the energy stored in the transformer T2 is completely delivered to the dc source. In addition, the dc source supplies energy to the load through T1. Due to the effect of E, iLm1 continues to increase linearly as (17).
At t10, S2 turns off. Half of the working stages of a switching period are completed. Due to the symmetrical configuration of the proposed converter, the analysis of the second half of the working stages is omitted.
C. Operation Principle at Light Load
At heavy load, the snubber capacitor voltage vCs is completely discharged to zero through the resonant process with the leakage inductance of the transformer during stage 3. However, at light load, the snubber capacitor has not yet been reduced to zero, while the current iD6 through D6 has been decreased to zero. In this case, the duration of stage 3 is expressed as:
(24)After the current iD6 through D6 decreases to zero, the snubber capacitor supplies the load. Under the effect of the load current Io, vCs decreases linearly as:
(25)Where vCs(t3) can be obtained by (8) and (24).
The snubber capacitor is discharged until t7. Then Cs begins to be resonantly charged. The difference between the maximum and minimum values of the snubber capacitor voltage vCs is obtained by integrating the load current:
(26)According to (26), at light load, the resonant charging current of the snubber capacitor in (21) changes as follows:
(27)According to (27), it can be observed that, under light load, the charging current of the snubber capacitor varies with the change of the load current. This means that the secondary circulating current is self-adjusted in accordance with the load condition.
Fig. 4. Waveforms of rectified voltage and filter current.
Ⅲ. STEADY-STATE CHARACTERISTICS OF THE CONVERTER
A. The Maximum Current Stress on Switches
Fig. 4 shows waveforms of the rectified voltage vd and output filter current iLd1 of the proposed converter and the output filter current iLt1 of the converter proposed in [25]. ∆ILd1 and ∆ILd1-re are the linear increment and resonant increment of the output filter current iLd1 in the proposed converter. Io is the output load current. Due to the very short commutation time of the current flowing through D5 (D6), Ds2 and Df, the current iLd1 of Ld1 satisfies the following equations:
(28)Because the average value of iLd1 of Ld1 is equal to the load current Io, the following equation is satisfied:
(29)From (29), iD6(t0) is approximately equal to:
(30)The linear increment ∆ILd1 is expressed as:
(31)iLd1(t7) is expressed as:
(32)∆Id is expressed as:
(33)The resonant increment ∆ILd1-re of the output filter current iLd1 is expressed as:
(34)According to Fig. 4, the following equations can be satisfied:
(35)According to (33) and (35), ∆Id1 and ∆Id2 are expressed as:
(36)From Fig. 4, it can be observed that:
(1) When ∆ILd1-re≤∆ILd1, the maximum current ISP of the switches S1~S4 appears at the turn-off instant of the switches S1 or S2:
(37)Where iLm2(t0) can be obtained by (38).
(38)According to (30), (37) and (38), ISP can be derived by:
(39)In this case, the current ripple ∆ILP is expressed as:
(40)(2) When ∆ILd1-re>∆ILd1, the maximum current ISP-re of the switches S1~S4 appears at the moment of 1/2 of a resonance period during stage 8:
(41)Where iLd1(t7) and ∆ILd1-re can be obtained by (32) and (34), respectively.
In this case, the current ripple ∆ILP is expressed as:
(42)According to the above analysis, when ∆ILd1-re≤∆ILd1+∆Id1, the maximum current stress on the switches of the proposed converter is less than or equal to that of the converter proposed in [25]. However, when ∆ILd1-re>∆ILd1+∆Id1, the maximum current stress on the switches of the proposed converter is higher than that of the converter proposed in [25].
Fig. 5 shows the effects of different coupled inductor turn ratios m and snubber capacitances Cs on ∆ILd1-re, ∆ILd1 and ∆Id1 under Io=10A. As shown in Fig. 5, when Cs and m increase, ∆ILd1-re and ∆Id1 increase. ∆ILd1 decreases with m increase. Selecting reasonable values of Cs and m can make the maximum current stress of the proposed converter smaller than that of the converter in [25].
Fig. 5. Current stress on switches under different coupled inductor turn ratios m and snubber capacitors Cs (Io=10A).
B. Output Voltage Characteristics
The output voltage Vo is equal to the average value of the voltage vd, which is rectified by the transformer secondary rectifier circuit. According to the waveform of vd depicted in Fig. 4, Vo is given by (43).
(43)In (43), the last part is the voltage drop caused by the transformer leakage inductance Ls. Since Ls is small enough, the last part can be neglected. Therefore, (43) can be changed as:
(44)Fig. 6 shows the effects of different coupled inductor turn ratios m on the output voltage characteristics under the following conditions of the open-loop control strategy, input voltage E=260V, load current Io=10A and snubber capacitor Cs=0.01μF. As shown in Fig. 6, when compared to the traditional ZVS ITSF converter, the linear relationship between the output voltage and the duty cycle D gets worse with the increasing of the coupled inductor turn ratio m. Therefore, the complexity of the closed-loop control strategy increases. When m＜0.3, the output voltage increases almost linearly with respect to duty cycle D increases. In addition, it is beneficial for closed-loop control.
|
(a) |
|
(b) |
Ⅳ. CONDITIONS TO ACHIEVE SOFT-SWITCHING
A. ZVS Condition for the Switches S1 and S2
tr is the duration from S1 turning off to the voltage of C1 rising to E. If the dead-time td meets tr ≤ td ≤ Th, the switches S1 and S2 realize ZVS turn-on. According to (1), (5) and (6), tr (see Fig. 2) is:
(45)From (45), to guarantee that S1 and S2 can achieve ZVS, the minimum load current is obtained as:
(46)Based on the above analysis, the parallel capacitors C1 and C2 can limit the turn-off voltage rise rates of S1 and S2, respectively. The turn-off voltage rise rate and the turn-off loss decrease as the parallel capacitance increases. However, a large parallel capacitance limits the ZVS range of S1 and S2. Thus, it is a trade-off between the turn-off switching losses and ZVS range of the switches S1 and S2 in the design for parallel capacitance.
B. ZCS Condition for the Switches S3 and S4
In order to achieve ZCS for the switches S3 and S4, the primary current must be reset to the magnetizing current before the switches S3 or S4 turn off. Thus, the reset time must meet the following constraint:
(47)treset is the duration of the iD6 decrease to zero under the effect of the coupled inductance and the snubber capacitance Cs. According to (11) and (14), treset can be derived as:
(48)Fig. 7 shows the characteristic of the reset time in the proposed converter and that of the converter in [25] under different coupled inductor turn ratios m and snubber capacitors Cs. As shown in Fig. 7, when compared with the converter in [25], the proposed converter effectively reduce the primary current reset time.
|
(a) |
|
(b) |
Fig. 8 illustrates the effects of the load current on the primary current reset time. Fig. 8(a) shows the variations of the primary reset times in the proposed converter and the converter in [25] with load current. In Fig. 8(a), tA is the reset time of the converter in [25], while tB is the reset time of the proposed converter. Their difference is ∆t= tA - tB. When compared with tA, the decrease ratio of tB is θ=∆t/tA. Fig. 8(b) shows the relationship between the load current and the decrease ratio θ. As shown in Fig. 8(b), when the load current decreases, the value of θ increases. This means that, under a light load, the decrease ratio of the primary current reset time is raised when the load current is reduced. This characteristic is beneficial to improve the efficiency of the converter under a light load.
|
(a) |
|
(b) |
C. Comparison of the Voltage and Current Stress on the Main Components among Different Converters
Table I shows the voltage and current stress on main components of the proposed converter, the conventional ZVS ITSF converter [22] and the ZVZCS ITSF converter using a coupled inductor [25].
The following conclusions can be drawn from Table I. (1) When ∆ILd1-re≤∆ILd1, the current stresses on switches and rectifier diodes of the proposed converter are lower than those of the ZVZCS ITSF converter in paper [25]. (2) The voltage stresses on the power switches of the three converters are identical. The voltage stresses on the rectifier diodes and freewheeling diodes in the proposed converter are higher than those of the conventional ZVS converter in [22] and the ZVZCS ITSF converter in [25].
|
|
Paper [22] |
Paper [25] |
The proposed ZVZCS ITSF converter |
|
| Voltage stress |
|
|
|
|
| Power switches |
E |
E |
E |
|
| Rectifier diodes |
2E/NT |
2E/NT |
3E/NT-Vo |
|
| Freewheeling diodes |
E/NT |
E/NT+VLt2 |
2(1+m)(E/NT-Vo)+Vo |
|
| Current stress |
|
|
∆ILd1-re≤ΔILd1 |
∆ILd1-re>∆ILd1 |
| Power switches |
|
|
|
|
| Rectifier diodes |
|
|
|
|
D. Maximum Effective Duty Cycle Deff-max
Due to the existence of the transformer leakage inductance, at t6, although the switches Q2 and S3 are both conducting, the primary current of the converter is not enough to provide the load current. During the period of [t6, t7], the rectifier diode and the freewheeling diodes are both conducting, and the secondary voltage of the transformer is clamped at mVo/(1+m). In this case, the voltages of [t6, t7] are lost in the secondary. The ratio of this duration and Th is Dloss. It is expressed as:
(49)Considering the ZCS realizing condition of the lagging switches and the duty cycle loss, the expression of the maximum effective duty cycle Deff-max is:
(50)Where Dreset=treset/Th. treset can be obtained by (48).
E. Parallel Capacitance, Coupled Ratio and Snubber Capacitance Design and Coupled Inductance Values Calculation
1) Parallel Capacitance Design: The parallel capacitance should satisfy the following two rules.
① The turn-off voltage rise rate of the leading switches should be lower than the given value of q. This value is set to q=5V/ns in this paper. According to (1):
(51)Where, Io-max=10A, NT=3.5. From (51), C should satisfy C>285pF.
② Two parallel capacitances can complete energy conversion during the dead time td=0.5μs, even under the condition of the lightest load. According to (45):
(52)Where, Io-min=2A, NT=3.5, E=260V. From (52), C should satisfy C＜549pF.
In summary, the range of the parallel capacitance is 285pF ＜C＜549pF. A 300pF capacitance, which includes the parasitic capacitor in the switch, is taken to parallel with the leading switches.
2) Coupled Ratio and Snubber Capacitance Design and Coupled Inductance Values Calculation: According to the previous theoretical analysis, to effectively minimize the loss produced by the primary current during the reset period, the faster the primary current is reset, the better the effect becomes. However, the coupled ratio m and snubber capacitance Cs increase. The current stress of the power switches and rectifier diodes increase accordingly.
Under the following conditions, input voltage E=260V, output voltage Vo=50V, turn ratio of the transformer NT=3.5 and rated load current Io=10A, the effects of different coupled ratios m and snubber capacitances Cs on the reset time treset and the maximum current ISP are shown in Fig. 9 and Fig. 10, respectively. From Fig. 9 and Fig. 10, it can be observed that with an increase in the coupled ratio and the snubber capacitor, the contribution for resetting the primary current is no more obvious than before. However, the current stress on the power switches and the rectifier diodes is increased. Moreover, the output voltage characteristic becomes worse.
Fig. 9. Effects of different coupled inductor turn ratios m and snubber capacitors Cs on the primary current reset time treset.
Fig. 10. Current stress of the power switches under different coupled ratios m and snubber capacitances Cs.
Therefore, the design of the coupled ratio m and the snubber capacitance Cs should satisfy the following two rules.
① m and Cs should make the lagging switches realize ZCS turn-off even under the condition of Deff-max.
② In order to satisfy the requirements of the converter on the current ripple ∆ILP of the output filter inductor, ∆ILP should be less than a given value.
For the sake of rule ①, according to (48) and (50), the primary current reset time treset should satisfy the inequality:
&bsp; (53)In order to correspond to rule ②, (40) should satisfy:
(54)Where p is the ripple rate of the current through the filter inductance Ld1.
From (31), Ld1 is:
(55)Since the coupled inductor shares a single core, the inductor Ld2 of the coupled inductor is:
(56)For example, assuming a rated output voltage of Vo=50V, the rated output current Io=10A, fs=100kHz, p=0.2, NT=3.5, Ls=0.3μH. Taking Deff-max=0.8, Dloss=0.1. From (53):
(57)From Fig. 9 and Fig. 10, it can be observed that, when the coupled ratio m≥0.1 and the snubber capacitor Cs≥6nF, the contribution for resetting the primary current is not very obvious. Nevertheless, when m≥0.15, the current stresses of the rectifier diodes and the power switches increase a lot. Therefore, the best parameters for the coupled ratio m are between 0.1 and 0.15. In this paper, m=0.1 is chosen. Then, according to (57), the snubber capacitor should satisfy Cs≥0.7nF. In this paper, Cs=6.8nF is chosen.
According to (48) and (49), Dreset≈0.037 and Dloss≈0.009 can be calculated, respectively. In this case, Dloss+Dreset+Deff-max≈0.846＜1. As a result, Cs=6.8nF and m=0.1 can satisfy the demand.
In order to make the current stress of the switches in the proposed converter less than that of the converter in [25], the proposed converter needs to satisfy ∆ILd1-re≤∆ILd1. According to (31) and (34), the coupled inductor Ld1 needs to satisfy the following inequality:
(58)Since the linear increment ∆ILd1 increases with a decrease of the coupling inductance, the current ripple also increases. Thus, ∆ILd1 is set at ∆ILd1≤0.1Io. According to (55), the following inequality is obtained:
(59)According to (58) and (59), the range of the coupled inductor Ld1 is 55μH≤Ld1≤154μH. In this paper, Ld1=120μH is chosen. From (56), Ld2=1.2μH. According to (40), ∆ILP=1.36＜pIo. Therefore, the set values of Ld1 and Ld2 satisfy the demand.
Ⅴ. SIMULATION AND EXPERIMENTAL RESULTS
In order to verify the validity of the aforementioned analysis, a 500W, 100kHz prototype has been built. The specifications of the prototype converter are given in Table II. A photo of the prototype converter is shown in Fig. 11.
| components |
parameters |
| E (Input voltage) |
260V |
| Vo (Output voltage) |
50V |
| f (Switching frequency) |
100kHZ |
| td(Dead time) |
0.5μs |
| S1~S4 (Switches) |
IPW65R065C7(650V, 33A) |
| D3, D4 (Primary diodes) |
DMUR3060WT (600V, 30A) |
| D5, D6 (Rectifier diodes) |
DMUR3060WT (600V, 30A) |
| Df, Ds1, Ds2 (Freewheeling and auxiliary diodes) |
DMUR1540 (400V, 15A) |
| NT (Transformer turn ratio) |
3.5:1 |
| Lm (Transformer magnetizing inductor) |
3mH |
| Ls(Transformer secondary leakage inductance) |
0.3μH |
| m (Coupled inductor turn ratio) |
0.1 |
| Ld1, Ld2 (Coupled inductance) |
120µH、1.2µH |
| C1, C2 (Parallel capacitance) |
300pF |
| Cs (Snubber capacitance) |
6.8nF |
| Co (Output capacitance) |
560µF |
Fig. 11. Photo of the prototype converter.
A. Waveform Evaluations
Fig. 12 and Fig. 13 show voltage and current waveforms of the leading switch S1 and the lagging switch S4 under a heavy load (Io=10A) and a light load (Io=2A), under E=260V, Vo=50V (Fig. 12(a) is a waveform of S1 under a heavy load. Fig. 12(b) is a waveform of S1 under a light load. Fig. 13(a) is a waveform of S4 under a heavy load. Fig. 13(b) is a waveform of S4 under a light load). From the obtained experimental results, it can be observed that waveforms of the power switches do not have the voltage or current spikes. In a wide load range, S1 turns off with pseudo-ZVS and turns on with ZVZCS. S4 turns off with near ZCS and turns on with pseudo-ZCS.
|
(a) |
|
(b) |
|
(a) |
|
(b) |
Fig. 14 shows voltage and current waveforms of the snubber capacitor under a heavy load (Io=10A) and a light load (Io=2A), under E=260V, Vo=50V (Fig. 14(a) is a waveform of Cs under a heavy load. Fig. 14(b) is a waveform of Cs under a light load). As shown in Fig. 14, the snubber capacitor is charged to the maximum value vCs-max during the supplying period, and it is discharged to supply the load during the resetting period. From Fig. 14(a), it can be observed that the snubber capacitance is completely discharged under a heavy load. However, Fig. 14(b) shows that the snubber capacitor is not completely discharged under a light load. Meanwhile, from Fig. 14(a) and (b), the charging current under a light load is obviously less than that under a heavy load, which means that the circulating current of the auxiliary circuit is self-adjusted to the load condition. Hence, the circulating current losses of the auxiliary circuit are reduced.
|
(a) |
|
(b) |
Fig. 15 shows current waveforms of the coupled filter inductor in the proposed converter and the converter of [25], under E=260V, Vo=50V, Io=10A, m=0.1, Cs=6.8nF. From Fig. 15, it can be observed that the converter in [25] has a serious parasitic ringing in the output filter inductor, which is produced by resonance among the transformer leakage inductance, the coupled inductor leakage inductance and the stray capacitors of the freewheeling diode and rectifier diode. However, as shown in Fig. 15, the proposed converter effectively suppresses parasitic ringing. This is because the proposed converter absorbs energy, which is then stored in the leakage inductances of transformer and coupled inductor, by the charging process of the snubber capacitance.
Fig. 15. The current waveforms of the coupled filter inductor (E=260V, f=100kHz, Vo=50V, Io=10A).
Fig. 16 compares waveforms of the rectifier voltage vd in the proposed converter and the converter in [25]. From Fig. 16, it can be observed that by using the reverse voltage of the coupled inductor and the charging voltage of the snubber capacitance, the proposed converter can effectively suppress the transient over-voltage and parasitic ringing in the secondary side of the transformer.
Fig. 16. Waveforms of the rectifier voltage vd (E=260V, f=100kHz, Vo=50V, Io=10A).
B. Dynamic Response Characteristic Evaluation
Fig. 17 shows the dynamic response of the output voltage for the proposed converter when the output load is switched under an output voltage of Vo=50V. Fig. 17(a) shows the output voltage response characteristic when the load is switched from a light load (Io=2A) to a heavy load (Io=10A) and from a heavy load to a light load in the steady state. From Fig. 17(a), it can be seen that the voltage amplitude fluctuates within ±0.8V and that the recovery time is within 1.2ms. Fig. 17(b) shows the output voltage response characteristic when the load is quickly switched. From Fig. 17(b), it can be seen that the voltage amplitude fluctuates within ±0.6V when the load is quickly switched. From Fig. 17, it can be seen that the proposed converter has good steady state and dynamic response characteristics.
|
(a) |
|
(b) |
C. Efficiency Evaluation
Fig. 18 shows the distribution of the theoretical calculated losses in the proposed converter, the ZVS converter in [22] and the ZVZCS converter in [25], under a rated output power of Po=500W. As shown in Fig. 18, the losses of the proposed converter produced by the switches Q1/Q2, the switches S3/S4, the rectifier diodes D5/D6, the freewheeling diode Df, and the auxiliary diode Ds1 and Ds2 are, 0.48W, 0.31W, 10.34W, 2.28W, 0.08W and 0.16W, respectively. When compared with the ZVZCS converter in [25], the loss saved by the leading switches Q1/Q2, the lagging switches S3/S4, the rectifier diodes D5/D6 and freewheeling diode Df are, 0.17W, 0.32W, 2.84W and 0.70W, respectively. The losses increased by the auxiliary diodes Ds1 and Ds2 are, 0.08W and 0.16W, respectively. In total, the losses are decreased by 3.79W. When compared with the ZVS converter in [22], the losses saved by the leading switches Q1/Q2, the lagging switches S3/S4 and the rectifier diodes D5/D6 are, 0.73W, 0.37W and 8.96W, respectively. The losses increased by the freewheeling diode Df, and the auxiliary diodes Ds1 and Ds2 are 2.28W, 0.08W and 0.16W, respectively. In total, the losses are decreased by 7.54W.
Fig. 18. Power loss analysis.
Fig. 19 illustrates actual power efficiency curves of the proposed converter and the ZVZCS converter in [25]. As shown in Fig. 19, in the full load range, the efficiency of the proposed converter is higher than that of the converter in [25]. In addition, the improved efficiency is more obvious with decreases in the load. The actual efficiency of the proposed converter can reach 95.2% at the rated load (500W). When compared with the ZVZCS converter in [25], the efficiency improved by nearly 1.2%. The actual power efficiency of the proposed converter is 94% under a light load (100W). When compared with the ZVZCS converter in [25], the efficiency is improved by nearly 3.2%.
Fig. 19. Experiment efficiency curves.
Ⅵ. CONCLUSION
In this paper, a ZVZCS interleaved two-switch forward converter using a simple passive auxiliary resonant circuit is presented. Moreover, this paper has analyzed the operation principle, steady state characteristics and soft-switching conditions of the proposed converter. According to a theoretical analysis and experimental research, the following conclusions can be summarized.
(1) The leading switches realize ZVS turn-off and ZVZCS turn-on. The lagging switches achieve ZCS turn-on and near ZCS turn-off.
(2) By increasing the turn-ratio of the coupled inductor, the proposed converter can accelerate the speed of resetting the primary current. Thus, this converter can achieve ZCS control in lagging switches more easily.
(3) The proposed converter can overcome the effects of the reverse recovery loss, the voltage stress and the parasitic ringing in the rectifier diodes. Therefore, the topology can be extended to heavy load applications.
(4) The circulating current of the auxiliary circuit can be automatically adjusted with the load, which is helpful for improving efficiency under a light load. Thus, this converter can maintain high power conversion efficiency in the full load range.
REFERENCES
[1] X. N. He, B. W. Williams, K. Sheng, S. J. Finney, and Z. M. Qian, “A composite soft switching circuit for power inverters,” APEC '99. Fourteenth Annual Applied Power Electronics Conference and Exposition. 1999 Conference Proceedings (Cat. No.99CH36285), Vol.2, pp. 1272-1278, 1999.
[2] F. M. Ibanez, J. M. Echeverria, D. Astigarraga, and L. Fontan, “Soft-switching forward DC–DC converter using a continuous current mode for electric vehicle applications,” IET Power Electronics, Vol. 8, No. 10, pp. 1978-1986, Sep. 2015.
[3] Y. H. Xi, P. K. Jain, Y. F. Liu, and R. Orr, “A self core reset and zero voltage switching forward converter topology,” IEEE Trans. Power Electron., Vol. 15, No. 6, pp. 1192- 1203, Nov. 2000.
[4] F. D. Tan, “The forward converter: from the classic to the contemporary,” in Proc. IEEE APEC Conf., Vol. 2, pp. 857-863, 2002.
[5] E. S. da Silva, E. A. A. Coelho, L. C. de Freitas, J. B. Vieira, and V. J. Farias, “A soft-single-switched forward converter with low stresses and two derived structures,” IEEE Trans. Power Electron., Vol. 19, No. 2, pp. 388-395, Mar. 2004.
[6] B. R. Lin, S. C. Tsay, and C. S. Yang, “Analysis and implementation of ZVS forward converter with centre- coupled rectifier,” IEE Proceedings-Electric Power Applications, Vol. 153, No. 5, pp. 642-652, Sep. 2006.
[7] M. Jinno, P. Y. Chen, and K. C. Lin, “An efficient active LC snubber for forward converters,” IEEE Trans. Power Electron., Vol. 24, No. 6, pp. 1522-1531, Jun. 2009.
[8] E. Adib and H. Farzanehfard, “Analysis and design of a zero-current switching forward converter with simple auxiliary circuit,” IEEE Trans. Power Electron., Vol. 27, No. 1, pp. 144-150, Jan. 2012.
[9] J. Y. Lin, W. Z. Tzeng, C. Y. Lin, C. F. Wang, and P. J. Liu, “Active-clamping forward converter with non-linear step-down conversion,” IET Power Electron., Vol. 8, No. 1, pp. 112-119, Jan. 2015.
[10] G. Waltrich and I. Barbi, “Modelling, control and realisation of the single-ended forward converter with resonant reset at the secondary side,” IET Power Electronics, Vol. 8, No. 11, pp. 2097-2106, Nov. 2015.
[11] J. P. Xu, X. H. Cao, and Q. C Luo, “An improved two- transistor forward converter,” in Proc. IEEE PEDS Conf., Vol. 1, pp. 225-228, 1999.
[12] M. Chen, D. H. Xu, and M. Matsui, “Study on magnetizing inductance of high frequency transformer in the two- transistor forward converter,” in Proc. IEEE PCC Conf., Vol. 2, pp. 597-602, 2002.
[13] Y. L. Gu, Z. Y. Lu, Z. M. Qian, X. M. Gu, and L. J. Hang, “A novel ZVS resonant reset dual switch forward DC–DC converter,” IEEE Trans. Power Electron., Vol. 22, No. 1, pp. 96-103, Jan. 2007.
[14] Y. K. Lo, T. S. Kao, and J. Y. Lin, “Analysis and design of an interleaved active-clamping forward converter,” IEEE Trans. Ind. Electron., Vol. 54, No. 4, pp. 2323-2332, Aug. 2007.
[15] B. R. Lin and H. K. Chiang, “Analysis and implementation of a soft switching interleaved forward converter with current doubler rectifier,” IET Electric Power Appl., Vol. 1, No. 5, pp. 697-704, Sep. 2007.
[16] K. B. Park, C. E. Kim, G. W. Moon, and M. J. Youn, “Three-switch active-clamp forward converter with low switch voltage stress and wide ZVS range for high-input- voltage applications,” IEEE Trans. Power Electron., Vol. 25, No. 4, pp. 889-898, Apr. 2010.
[17] K. B. Park, G. W. Moon, and M. J. Youn, “Two-switch active-clamp forward converter with one clamp diode and delayed turnoff gate signal,” IEEE Trans. Ind. Electron., Vol. 58, No. 10, pp. 4768-4772, Oct. 2011.
[18] A. Coban and I. Cadirci, “Active clamped two-switch forward converter with a soft switched synchronous rectifier,” IET Power Electron., Vol. 4, No. 8, pp. 908-918, Sep. 2011.
[19] K. Soltanzadeh, M. Dehghani, and H. Khalilian, “Analysis, design and implementation of an improved two-switch zero-current zero-voltage pulse-width modulation forward converter,” IET Power Electron., Vol. 7, No. 4, pp. 1016- 1023, Apr. 2014.
[20] M. T. Zhang, M. M. Jvanovic, and F. C. Lee, “Analysis and evaluation of interleaving techniques in forward converters,” IEEE Trans. Power Electron., Vol. 13, No. 4, pp. 690-698, Jul. 1998.
[21] Y. F.Chen and L. G. He, “An interleaved series-parallel combination of two-transistor forward converters,” in Proc. IEEE ICIEA Conf., pp. 1-5, 2006.
[22] H. S. Kim, H. W. Seong, K. B. Park, H. S. Youn, G. W. Moon, and M. J. Youn, “Zero-voltage-switching interleaved two-switch forward converter with phase-shift control,” in Proc. IEEE Energy Conversion Congress and Exposition, pp. 3727-3732, 2010.
[23] H. Feng, D. H. Xu, and M. Matsui, “A novel ZVT circuit for interleaving two-transistor forward converter,” in Proc. IEEE APEC Conf., Vol. 2, pp. 754-759, 2000.
[24] D. de Souza Oliveira Jr., C. E. de Alencar e Silva, R. P. Torrico-Bascope, F. L. Tofoli, C. A. Bissochi Jr., J. B. Vieira Jr., V. J. Farias, and L. C. de Freitas, “Analysis, design, and experimentation of a double forward converter with soft switching characteristics for all switches,” IEEE Trans. Power Electron., Vol. 26, No. 8, pp. 2137-2148, Aug. 2011.
[25] S. Hamada and M. Nakaoka, “A novel zero-voltage and zero-current switching PWM DC-DC converter with reduced conduction losses,” IEEE Trans. Power Electron., Vol. 17, No. 3, pp. 413-419, May 2002.
[26] S. Hamada and M. Nakaoka, “Analysis and design of a saturable reactor assisted soft-switching full-bridge DC-DC converter,” IEEE Trans. Power Electron., Vol. 9, No. 3, pp. 309-317, May 1994.
Enhui Chu received his M.S. degree in Automation from Northeastern University, Shenyang, China, in 1993; and his Ph.D. degree in Electrical Engineering from Yamaguchi University, Yamaguchi, Japan, in 2002. From 1997 to 1999, he was a Visiting Scholar and a Researcher at Yamaguchi University. From 2003 to 2006, he was a researcher in Yutaka Electric Mfg. Co., Ltd. of the Nippon Steel and Sumitomo Metal Corporation, Konan, Japan. Since 2006, he has been with the College of Information Science and Engineering, Northeastern University, Shenyang, China, where he is presently working as a Professor. His current research interests include power converters, medical electronics, auto- electronics, soft-switching techniques, and the application of soft-switching techniques in renewable energy power conversion systems.
Jianqun Bao received her B.S. degree in Electrical Engineering and Automation from Northeastern University, Shenyang, China, in 2017, where she is presently working towards her M.S. degree in Electrical Engineering. Her current research interests include PWM DC/DC converters and soft-switching technology.
Qi Song received his B.S. degree from the Zhengzhou University of Light Industry, Zhengzhou, China, in 2017. He is presently working towards his M.S. degree in Electrical Engineering at Northeastern University, Shenyang, China. His current research interests include PWM DC/DC converters and soft- switching technology.
Yang Zhang received his B.S. degree in Electrical Engineering and Automation at the North China University of Science and Technology, Tangshan, China, in 2017. He is presently working towards his M.S. degree in Electrical Engineering at Northeastern University, Shenyang, China. His current research interests include PWM DC/DC converters and soft-switching technology.
Haolin Xie received his B.S. degree in Automation from Northeastern University, Shenyang, China, in 2017, where he is presently working towards his M.S. degree in Electrical Engineering. His current research interests include high-performance inverters and soft-switching techniques.
Zhifang Chen received his B.S. degree in Electrical Engineering and Automation from Northeastern University, Shenyang, China, in 2018, where he is presently working towards his M.S. degree in Electrical Engineering. His current research interests include high- performance inverters and soft-switching techniques.
Yue Zhou received his B.S. degree in Electrical Engineering and Automation from the Jiangsu University of Science and Technology, Zhenjiang, China, in 2018. He is presently working towards his M.S. degree in Electrical Engineering at Northeastern University, Shenyang, China. His current research interests include high-performance inverters and soft-switching techniques.