사각형입니다.

https://doi.org/10.6113/JPE.2019.19.6.1496

ISSN(Print): 1598-2092 / ISSN(Online): 2093-4718



Scheme for Reducing Harmonics in Output Voltage of Modular Multilevel Converters with Offset Voltage Injection


Devnath Anupom*, Dong-Cheol Shin*, and Dong-Myung Lee


†,*School of Electronic and Electrical Engineering, Hongik University, Seoul, Korea



Abstract

This paper proposes a new THD reduction algorithm for modular multilevel converters (MMCs) with offset voltage injection operated in nearest level modulation (NLM). High voltage direct current (HVDC) is actively introduced to the grid connection of offshore wind powers, and this paper deals with a voltage generation technique with an MMC for wind power generation. In the proposed method, third harmonic voltage is added for reducing the THD. The third harmonic voltage is adjusted so that each of the pole voltage magnitudes maintains a constant value with a maximum number of (N+1) levels, where N is the number of sub-modules per arm. By using the proposed method, the THD of the output voltage is mitigated without increasing the switching frequency. In addition, the proposed method has advantageous characteristics such as simple implementation. As a part of this study, this paper compares the THD results of the conventional method and the proposed method with offset voltage injection to reduce the THD. In this paper, simulations have been carried out to verify the effectiveness of the proposed scheme, and the proposed method is implemented by a HILS (Hardware in the Loop Simulation) system. The obtained results show agreement with the simulation results. It is confirmed that the new scheme achieved the maximum level output voltage and improved the THD quality.


Key words: High voltage direct current (HVDC) transmission, HILS (Hardware in the Loop Simulation), Modulation index (MI), Modular multilevel converter (MMC), Nearest level modulation (NLM), Sub-module (SM), Third harmonics, Total harmonic distortion (THD)


Manuscript received Jun. 1, 2019; accepted Aug. 26, 2019

Recommended for publication by Associate Editor Younghoon Cho.

Corresponding Author: dmlee@hongik.ac.kr Tel: +82-2-320-3047, Hongik University, Seoul, Korea

*School of Electronic and Electrical Eng., Hongik University, Korea



Ⅰ. INTRODUCTION

The modular multilevel converter (MMC) was first introduced in 2001 as a new type of voltage source converter (VSC) [1]. After its introduction, many researchers have been focused on the technical challenges corresponding with the design, operation and control of the MMC to develop its performance for numerous applications: VSC based transmission [2]. Due to its good modularity, efficiency, flexible scalability, better harmonic performance and excellent quality waveforms, the MMC has received a great deal of attention in the function of HVDC transmission, reactive power compensation, motor drives, electric railways, etc. Now, it is hot topic in HVDC research and construction.

Recently, the introduction of large capacity offshore wind power has been expanding due to developments in new and renewable energy. HVDCs are being introduced for linking systems. The MMC is well known as the most applicable and proficient type of converter For the HVDC systems associating with offshore wind farms and MVDC systems [3].

In the grid connection of offshore wind power generation systems, two MMCs use the back to back structure. This study is concerned with sharing the generator voltage of an offshore wind turbine among two MMC’s. In this study, a THD reduction technique is proposed for the generated output voltage of the MMC that works as the source voltage of a wind turbine.

Meanwhile, voltage generation through an MMC can be broadly divided into pulse width modulation (PWM) and staircase modulation. When the SM number is relatively small, PWM is usually used since it can make the output voltage of an MMC achieve an excellent quality [4]. However, the disadvantage is a high power loss. On the other hand, since NLM is simpler and the switching frequency is lower, it is recommended for a large number of SMs so that the output quality is good enough [5].

Hybrid topology of an MMC can be for enlarging the output voltage level [6]. However, it makes the highest THD which is a serious threat to the reliable operations of MMC systems and creates a more complication of MMC topology. That is why NLM is the best solution for overcoming the above mentioned problem.

When the operational level is low, the THD of the output voltage is rather high. Meanwhile the operational level should be controlled by  changing the modulation index (MI). Moreover, an MMC in an MVDC is more formed because of the small number of SMs [7].

Methods for reducing the THD have been proposed by several researchers [8]-[10]. In [8], Li et al, proposed a method combining PWM and NLM for improving the output voltage and reducing the THD. However, this method substantially increases the switching frequency of IGBTs. The method proposed in [9] can increase the output voltage level without increasing the THD. However, it leads to a change of the average voltage of the sub-module capacitor. Therefore, it results in an amplitude change of the output voltage. Some harmonic elimination methods were presented in [10], [11]. However, they require more calculations, which results in lower modularity of MMCs. The authors of [12], [13] presented a strategy to determine the switching angles that minimizes the THD with analytically proof. However, the MI is restricted in the zone close to its upper bound, making it inappropriate for applications with various voltage level requirements or unstable load conditions. Moreover, the calculation complexity of these techniques is high and they are troublesome to implement in real time simulations. More importantly, the reducing THD becomes a common concern for sensitive industries and HVDC applications.

The proposed method has a simple and effective way to overcome these problems. The MMC is operated in NLM to reduce the total harmonic distortion (THD) of the pole voltage and to generate the maximum level of pole voltage by adding the third harmonic voltage. Moreover, this paper compares the performances of several methods that aim to reduce THD by adding offset voltage.

This paper is organized as follows. In Section II, the operational characteristics of an MMC are introduced. A comparison of different modulation methods that uses offset voltage injection is analyzed in Section III. Simulation and experimental results are presented in Section IV and section V, respectively. Finally, some conclusions are presented in Section VI.


Fig. 1. Diagrams. (a) Topology of a single phase MMC. (b) Sub- module structure. (c) Equivalent circuit of an MMC.

그림입니다.
원본 그림의 이름: image1.png
원본 그림의 크기: 가로 379pixel, 세로 482pixel

(a)

그림입니다.
원본 그림의 이름: image2.png
원본 그림의 크기: 가로 263pixel, 세로 218pixel

(b)

그림입니다.
원본 그림의 이름: image3.png
원본 그림의 크기: 가로 281pixel, 세로 122pixel

(c)



Ⅱ. OPERATIONAL CHARACTERISTICS OF AN MMC


A. Output Voltage Forming

Fig. 1(a) shows the configuration of a single phase MMC, which consists of two arms. Each arm includes a total of 그림입니다.
원본 그림의 이름: CLP0000184c2bee.bmp
원본 그림의 크기: 가로 119pixel, 세로 73pixel sub-modules and two arm reactors. Two arms in the same phase form a phase unit.

Fig. 1(b) shows an SM structure. For commercial HVDC systems, a SM configured with a half bridge is very popular. Each SM is a simple chopper cell composed of two insulated-gate bipolar transistor (IGBT) switches, two anti- parallel diodes and a capacitor.

The SM output voltage 그림입니다.
원본 그림의 이름: CLP0000184c0001.bmp
원본 그림의 크기: 가로 132pixel, 세로 69pixel only has two values: 그림입니다.
원본 그림의 이름: CLP0000184c0002.bmp
원본 그림의 크기: 가로 235pixel, 세로 81pixel when the upper IGBT is switched on and the lower one is switched off; or 그림입니다.
원본 그림의 이름: CLP0000184c0003.bmp
원본 그림의 크기: 가로 220pixel, 세로 103pixel when the lower IGBT is switched on and the upper one is switched off. This means that each SM only has two conditions in normal operation: switched on or off.

Upper arm and lower arm voltage equations in single phase are shown as follows.

그림입니다.
원본 그림의 이름: CLP0000184c0004.bmp
원본 그림의 크기: 가로 649pixel, 세로 166pixel          (1)

그림입니다.
원본 그림의 이름: CLP0000184c0005.bmp
원본 그림의 크기: 가로 650pixel, 세로 178pixel         (2)

where, u is voltage of a single phase. In addition, 그림입니다.
원본 그림의 이름: CLP0000184c000a.bmp
원본 그림의 크기: 가로 90pixel, 세로 99pixel and 그림입니다.
원본 그림의 이름: CLP0000184c000b.bmp
원본 그림의 크기: 가로 78pixel, 세로 88pixel are the voltages of the upper arm and the lower arm, respectively. The current in a single phase is:

그림입니다.
원본 그림의 이름: CLP0000184c0006.bmp
원본 그림의 크기: 가로 272pixel, 세로 122pixel          (3)

where, 그림입니다.
원본 그림의 이름: CLP0000184c000c.bmp
원본 그림의 크기: 가로 57pixel, 세로 94pixel, 그림입니다.
원본 그림의 이름: CLP0000184c000d.bmp
원본 그림의 크기: 가로 61pixel, 세로 90pixel and 그림입니다.
원본 그림의 이름: CLP0000184c000e.bmp
원본 그림의 크기: 가로 72pixel, 세로 100pixel are the phase current, upper arm and lower arm current, respectively.

The upper arm current is the total of half the phase current 그림입니다.
원본 그림의 이름: CLP0000184c000f.bmp
원본 그림의 크기: 가로 91pixel, 세로 105pixel, one third of the DC current 그림입니다.
원본 그림의 이름: CLP0000184c0010.bmp
원본 그림의 크기: 가로 89pixel, 세로 98pixel and the circulating current in the phase 그림입니다.
원본 그림의 이름: CLP0000184c0011.bmp
원본 그림의 크기: 가로 98pixel, 세로 105pixel.

그림입니다.
원본 그림의 이름: CLP0000184c0007.bmp
원본 그림의 크기: 가로 542pixel, 세로 188pixel                  (4)

그림입니다.
원본 그림의 이름: CLP0000184c0008.bmp
원본 그림의 크기: 가로 559pixel, 세로 196pixel           (5)

The common circulating current 그림입니다.
원본 그림의 이름: CLP0000184c0012.bmp
원본 그림의 크기: 가로 95pixel, 세로 123pixel can be represented by equation (6).

그림입니다.
원본 그림의 이름: CLP0000184c0009.bmp
원본 그림의 크기: 가로 577pixel, 세로 211pixel         (6)

The circulating current does not influence the DC and AC part of the circuit. However, it does cause an increase in the arm current and the voltage ripple of the capacitors. The terminal voltage 그림입니다.
원본 그림의 이름: CLP0000184c0013.bmp
원본 그림의 크기: 가로 95pixel, 세로 103pixel can be expressed by equations (7) and (8).

그림입니다.
원본 그림의 이름: CLP0000184c0014.bmp
원본 그림의 크기: 가로 1009pixel, 세로 219pixel         (7)

그림입니다.
원본 그림의 이름: CLP0000184c0015.bmp
원본 그림의 크기: 가로 1037pixel, 세로 182pixel          (8)

Equation (9) is obtained by adding equations (7) and (8).

그림입니다.
원본 그림의 이름: CLP0000184c0016.bmp
원본 그림의 크기: 가로 936pixel, 세로 193pixel   (9)

Based on equation (9), the arm reactor plays an important role for the voltage drop.

그림입니다.
원본 그림의 이름: CLP0000184c0017.bmp
원본 그림의 크기: 가로 81pixel, 세로 79pixel is the electromotive force (EMF) and is expressed as following equation (10).

그림입니다.
원본 그림의 이름: CLP0000184c0018.bmp
원본 그림의 크기: 가로 395pixel, 세로 194pixel            (10)

In general, the ac EMF reference value is simplified as equation (11).

그림입니다.
원본 그림의 이름: CLP0000184c0019.bmp
원본 그림의 크기: 가로 659pixel, 세로 200pixel         (11)

where MI is the modulation index, and 그림입니다.
원본 그림의 이름: CLP0000184c001f.bmp
원본 그림의 크기: 가로 77pixel, 세로 69pixel is the angular frequency.

An equivalent circuit of the MMC is shown in Fig. 1(c). From (1), (2) and (3), the output voltage can be written as

그림입니다.
원본 그림의 이름: CLP0000184c001a.bmp
원본 그림의 크기: 가로 641pixel, 세로 188pixel            (12)

With the traditional NLM method, N sub-modules are inserted into the circuit. Therefore, the equation (13) is supported the dc side.

그림입니다.
원본 그림의 이름: CLP0000184c001b.bmp
원본 그림의 크기: 가로 394pixel, 세로 141pixel           (13)


B. Modulation Analysis

Generally, pulse width modulation (PWM) and staircase modulation are two common modulation techniques. Using various modulation methods, PWM is based on regulating all the sub-module capacitor voltages. Staircase modulation is based on a sorting technique to control voltages. Staircase modulation has a lower switching frequency, and the developed output voltage changes less suddenly. PWM is usually used when the number of SMs in the MMC is relatively small since this can make the output voltage of the MMC having an excellent quality. However, it suffers due to a great loss of power. On the other hand, the staircase modulation SM is easy to calculate and has a lower power loss. However, the quality of voltage is not good when the number of SMs in the MMC is comparatively small. The equal area method (EAM) [14], selective harmonic reduction method (SHRM)[15], and nearest level modulation (NLM) method are common staircase modulation schemes. The EAM and SHRM schemes develop comparatively low level harmonics. However, they need more calculations. That is why NLM is one of the most commonly used staircase modulation schemes.

NLM works by using a rounding function to select the level changing point, and it avoids the use of triangular waves in the output voltage. Thus, it possesses uncomplicated calculations and easy implementation.

When an MMC operates in the NLM, 그림입니다.
원본 그림의 이름: CLP0000184c0020.bmp
원본 그림의 크기: 가로 78pixel, 세로 89pixel is the peak value of the inner alternating voltage, and MI is calculated by the relation of the AC voltage and the DC voltage.

그림입니다.
원본 그림의 이름: CLP0000184c001c.bmp
원본 그림의 크기: 가로 302pixel, 세로 279pixel         (14)

The upper and lower arms reference voltages can be expressed by using the trigonometric function along with modulation index as shown in equations (15) and (16).

그림입니다.
원본 그림의 이름: CLP0000184c001d.bmp
원본 그림의 크기: 가로 681pixel, 세로 190pixel          (15)

그림입니다.
원본 그림의 이름: CLP0000184c001e.bmp
원본 그림의 크기: 가로 694pixel, 세로 181pixel         (16)

Fig. 2 shows an overall diagram of the NLM method using the rounding function and the reduced switching frequency voltage balancing algorithm. The number of sub-modules is determined by loading the command of the upper and lower arm reference voltage.


그림입니다.
원본 그림의 이름: image33.png
원본 그림의 크기: 가로 562pixel, 세로 117pixel

Fig. 2. Overall diagram of the NLM method.


The voltage level plays an important role in NLM because it impacts on the average switching time and the output voltage THD. The THD of the output voltage is designated by equation (17).

그림입니다.
원본 그림의 이름: CLP0000184c0021.bmp
원본 그림의 크기: 가로 646pixel, 세로 342pixel       (17)

where, 그림입니다.
원본 그림의 이름: CLP0000184c0022.bmp
원본 그림의 크기: 가로 186pixel, 세로 103pixeland 그림입니다.
원본 그림의 이름: CLP0000184c0023.bmp
원본 그림의 크기: 가로 275pixel, 세로 127pixel are the RMS voltage of the nth harmonic and the fundamental harmonics, respectively.

When the voltage level and modulation index increase, the THD can be minimized. However, it reduces nonlinearly in a definite range, which is due to the level of the voltage casually changing because of the MI. Fig. 3 shows THD results when the maximum voltage level is designated to 10~50, and the scale of the MI is set at 그림입니다.
원본 그림의 이름: CLP0000184c0024.bmp
원본 그림의 크기: 가로 307pixel, 세로 73pixel. If the voltage level is more than 50, the output voltage THD stays as small as less than 2%. By using sine PWM with equations (15) and (16), the THD with respect to the MI corresponding to different level numbers of MMCs is shown in Fig. 3.


그림입니다.
원본 그림의 이름: image38.png
원본 그림의 크기: 가로 728pixel, 세로 457pixel

Fig. 3. THD with respect to the MI according to the number of SMs.



Ⅲ. PROPOSED METHOD FOR REDUCING THE THD IN THE OUTPUT VOLTAGE

This paper proposes a new scheme that compensates the decrease of the output voltage level due to a low MI. The proposed method decreases the total harmonic distortion (THD) of the pole voltage corresponding with the magnitude of the MI.

In this method, the third harmonic voltage plays an important role to control the phase voltage to obtain the maximum pole voltage. The maximum level pole voltage shows the lowest THD. Moreover, a triangular waveform by the Fourier series consists of a number of harmonics whereas a sinusoidal waveform only consists of one frequency component. Due to the sinusoidal waveform of the third harmonic, it also helps reduce the THD of the output voltage.

The proposed method operated with the third harmonic voltage having a sinusoidal waveform, which is explained by equation (18).

그림입니다.
원본 그림의 이름: CLP0000184c0025.bmp
원본 그림의 크기: 가로 398pixel, 세로 126pixel        (18)

그림입니다.
원본 그림의 이름: CLP0000184c0026.bmp
원본 그림의 크기: 가로 485pixel, 세로 158pixel      (19)

Where α is a variable with respect to a variable modulation index. It can be conceived by using the maximum value equation of the pole voltage. The value of α has been evaluated in the zone of 그림입니다.
원본 그림의 이름: CLP0000184c0027.bmp
원본 그림의 크기: 가로 261pixel, 세로 68pixel, where the pole voltage, due to the third harmonic voltage injection, is greater than the phase voltage.

By using equations (15) and (16), the reference voltage is determined according to the value of the MI, and if NLM is applied as shown in Fig. 2, the number of pole voltage levels can be calculated. Therefore, the offset voltage in equation (18) is applied and follows equation (19). Therefore, the pole voltage command value becomes 그림입니다.
원본 그림의 이름: CLP0000184c0028.bmp
원본 그림의 크기: 가로 93pixel, 세로 120pixel and the maximum number of voltage levels is generated. As a result, the THD is reduced.


그림입니다.
원본 그림의 이름: image44.png
원본 그림의 크기: 가로 817pixel, 세로 452pixel

Fig. 4. Pole, phase and third harmonic voltages.


Fig. 4 shows the pole voltage, phase voltage and harmonic. The pole voltage always stands at the maximal value in the phase angle of 그림입니다.
원본 그림의 이름: CLP0000184c0029.bmp
원본 그림의 크기: 가로 178pixel, 세로 119pixel. It can be initiated by applying the pole voltage’s maximum value equation.

Equations (20)-(22) express the phase voltage with the MI and the DC voltage.

그림입니다.
원본 그림의 이름: CLP0000184c002a.bmp
원본 그림의 크기: 가로 587pixel, 세로 171pixel               (20)

그림입니다.
원본 그림의 이름: CLP0000184c002b.bmp
원본 그림의 크기: 가로 744pixel, 세로 183pixel            (21)

그림입니다.
원본 그림의 이름: CLP0000184c002d.bmp
원본 그림의 크기: 가로 743pixel, 세로 171pixel            (22)

Third harmonic equation with the MI and the DC voltage.

그림입니다.
원본 그림의 이름: CLP0000184c002e.bmp
원본 그림의 크기: 가로 799pixel, 세로 180pixel           (23)

그림입니다.
원본 그림의 이름: CLP0000184c002f.bmp
원본 그림의 크기: 가로 218pixel, 세로 113pixel and 그림입니다.
원본 그림의 이름: CLP0000184c0030.bmp
원본 그림의 크기: 가로 203pixel, 세로 113pixel support equation (23) and the difference is just the phase shift.

The following formula defines the greatest value of the pole voltage. 그림입니다.
원본 그림의 이름: CLP0000184c0031.bmp
원본 그림의 크기: 가로 63pixel, 세로 58pixel can be calculated by equation (24).

그림입니다.
원본 그림의 이름: CLP0000184c0032.bmp
원본 그림의 크기: 가로 1187pixel, 세로 183pixel

그림입니다.
원본 그림의 이름: CLP0000184c0033.bmp
원본 그림의 크기: 가로 813pixel, 세로 159pixel             (24)

Fig. 5 shows the proposed algorithm for offset voltage control including the NLM. The phase voltage reference is set through sensing the voltage. α is determined in accordance with the value of the MI and follows equation (24). The offset voltage and pole voltage references are expressed by equations (18) and (19), respectively. The pole voltage reference is passed through the NLM algorithm to achieve the switching pulses. For real-time operation, a digital signal processor (DSP) board can freely implement the proposed algorithm on since it does not demand a huge running period.


그림입니다.
원본 그림의 이름: image58.png
원본 그림의 크기: 가로 291pixel, 세로 395pixel

Fig. 5. Flowchart of the proposed method.



Ⅳ. COMPARISON OF MODULATION SCHEMES THAT UTILIZE OFFSET VOLTAGE INJECTION

In terms of THD reduction through setting the maximum voltage level by injecting offset voltage [16], there are a number of modulation schemes available. Some of them are listed below and their results are compared with the THD results of the proposed method.


A. Modulation Analysis

1) Modulations with Offset Voltage Injection

The pole voltage 그림입니다.
원본 그림의 이름: CLP0000184c0034.bmp
원본 그림의 크기: 가로 152pixel, 세로 92pixel is a summation of the phase voltage 그림입니다.
원본 그림의 이름: CLP0000184c0035.bmp
원본 그림의 크기: 가로 142pixel, 세로 93pixel and the offset voltage 그림입니다.
원본 그림의 이름: CLP0000184c0036.bmp
원본 그림의 크기: 가로 87pixel, 세로 77pixel.

그림입니다.
원본 그림의 이름: CLP0000184c0037.bmp
원본 그림의 크기: 가로 520pixel, 세로 122pixel        (25)

For applying the offset voltage control modulation, the relationship between the prime values of the maximum and the minimum pole voltages can be made equivalent by equation (26) and offset voltage is identified by equation (27). Where, 그림입니다.
원본 그림의 이름: CLP0000184c0036.bmp
원본 그림의 크기: 가로 87pixel, 세로 77pixel has a well-known triangular shape.

그림입니다.
원본 그림의 이름: CLP0000184c0038.bmp
원본 그림의 크기: 가로 746pixel, 세로 146pixel          (26)

그림입니다.
원본 그림의 이름: CLP0000184c0039.bmp
원본 그림의 크기: 가로 541pixel, 세로 203pixel          (27)

In this modulation, the MMC output voltage level decreases, and the output voltage level is dependent on the phase voltage magnitude (i.e. MI).


2) Offset Voltage Control Modulation

There is another method for obtaining the maximum output voltage level. This method uses equation (28) for controlling the offset voltage. In this method, the shape of 그림입니다.
원본 그림의 이름: CLP0000184c0036.bmp
원본 그림의 크기: 가로 87pixel, 세로 77pixel is a scaled triangular waveform.

그림입니다.
원본 그림의 이름: CLP0000184c003a.bmp
원본 그림의 크기: 가로 623pixel, 세로 202pixel          (28)

where, α is variable that is controlled by changing the modulation index.


3) Third Harmonic Voltage Control Method

By using the third harmonic method, the pole voltage is the summation of the phase voltage and the third harmonic voltage 그림입니다.
원본 그림의 이름: CLP0000184c003b.bmp
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Moreover, equation (30) can simplify the relationship between the third harmonic and the phase voltage.

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In this modulation, the output voltage level depends on the phase voltage magnitude, and the THD result is not better in the expected modulation index range.



Ⅴ. SIMULATION RESULTS

To verify the performance of the proposed modulation method, a detailed model is developed and simulations are carried out with MATLAB/Simulink. The circuit parameters for the simulation model are presented in Table I.


TABLE I CIRCUIT PARAMETERS FOR SI MULATION STUDY

Parameters 

Values

DC bus Voltage

690 V

Arm Inductor

3.00 mH

SM Capacitor

7.5 mF

Frequency

60 Hz

Line Inductance

1.00 mH

Modulation Index

0.9

Number of SM

30


Table II summarizes comparison results for four different modulation schemes. The proposed method maintains a constant maximum pole voltage level. This grants the lowest THD of the pole voltage and ripple reduction of the SM capacitor voltage.


TABLE II COMPARISON OF DIFFERENT MODULATION SCHEMES

Items

Only offset

α offset method

Using third harmonic

Proposed method

Main Function

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Maximum Phase Voltage

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Maximum Pole Voltage

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THD

Greatest

Lower

Greater

Lowest


Fig. 6 presents a comparison between the third harmonic method and the proposed method. What is interesting is that the pole voltage is higher in the proposed method than in the third harmonic injection method in Fig. 6(a).


Fig. 6. Performance analysis of two schemes. (a) Third harmonic injection method. (b) Proposed method.

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(a)

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(b)


Moreover, in third harmonic injection method, the peak value of the phase voltage is not constant which is responsible for reducing the voltage level. On the other hand, Fig. 6(b) shows that the proposed scheme generates the pole voltage at its greatest value, which is half of the DC voltage. Therefore, the output voltage is generated with (N+1) levels.

In order to increment the pole voltage magnitude so that is larger than the phase voltage, the third harmonic voltage is added. These waveforms ensure that the pole has a constant maximum level. Because there are more levels in the pole voltage of the proposed method, the THD result shows more improvement than the third harmonic method.


A. THD Results

For the MMC the peak AC side phase voltage can never exceed half of the DC side pole voltage. In other words, the modulation index is limited to the interval 그림입니다.
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In addition, they pointed out that the modulation index is smaller than 1, and that a design with a larger capacitor voltage can result in a higher penalty. From the above discussion, it can be seen that in a wind turbine based power system, the modulation index range is approximately 0.8~0.95.

In this range, the proposed method shows the lowest THD results for the phase voltage and line to line voltage. This can be seen in Fig. 7.


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Fig. 7. Phase voltage THD analysis results for four modulation schemes.


Fig. 7 depicts the THD values of the phase voltage for four modulation schemes with respect to different modulation indexes. The phase voltage THD is inversely proportional to the MI.

From Fig. 7, it can be seen that there are several fluctuations in the THD values with respect to the MI by using only the offset voltage injection method and only the third harmonic addition method. Due to fluctuations in the THD results with respect to the MI, only the third harmonic and only the offset voltage injection methods are not suitable for wind turbine applications.

In addition, Fig. 7 shows that the proposed (alpha harmonic) method has a lower THD in the expected modulation index range than the alpha offset method.

Thus, it can be concluded that for wind power application that worked about the upper mentioned modulation index range (0.8~0.95), the proposed method shows a lower THD than the other three methods. Moreover, in the proposed method, the THD value always decreases with an increment of the MI. These phenomena are not present in other three methods.

Harmonic components are shown in Fig. 8. The results show that the fifth, seventh and eleven harmonics of the line voltage are very short in magnitude. Because of the 120-degree phase shift among the phase voltages, all of the triplen harmonics in the line voltage are very small.


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Fig. 8. Magnitude (% fundamental) and harmonic order.



Ⅵ. EXPERIMENTAL RESULTS

To validate the efficacy of the proposed method, experiments were carried out with a HILS (Hardware in the Loop Simulation) system. For experimental results, a scaled hardware prototype was assembled in the lab.

In Fig. 9 some devices are shown for the setup including an OP4510 RT-LAB ① for real time simulation, a control board with a FPGA ②, a signal interface board ③, a voltage regulator for making 3.3V ④, and a power supply ⑤.


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Fig. 9. Experimental setup.


An MMC model made by Simulink is implemented in the Real Time OS ① and the controller with a FPGA ② make output voltages for a wind turbine with the proposed offset voltage adjustment method.

Fig. 10 shows experimental waveforms of the pole voltage, phase voltage and third harmonic voltage when the MMC is operated at 31-levels. After the third harmonic injection, the pole voltage changes. Simulation results and experimental waveforms confirm that after injecting alpha harmonics the pole has a level of Vdc/2, which is the maximum pole voltage. Thus, the THD results show a better improvement.


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Fig. 10. Experimental waveform of the pole, phase, and harmonic voltages.


Fig. 11 shows the changes in the arm voltage after the alpha harmonic injection. After the alpha harmonic injection, the arm voltage maintains the maximum peak value which is the same as the DC bus voltage.


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Fig. 11. Experimental waveform of the arm voltage.


Fig. 12(a) shows an experimental waveform of the pole voltage, which is regulated in terms of magnitude and phase.


Fig. 12. Experimental waveforms. (a) Pole voltage. (b) THD value.

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(a)

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(b)


After the alpha harmonic injection, the pole voltage level has changed and reached the peak value. Moreover, after the alpha harmonic injection, the generated pole voltage is more linear than before. Fig. 12(b) shows the amount of change in the THD value after injecting the alpha harmonic.

In proposed system, the alpha harmonic injection time is 6.3 sec. Before the alpha harmonic injection, the THD of the pole voltage is 3.42%. After the alpha harmonic injection, the THD of pole voltage becomes 2.34%, which is a 31% reduction in the THD.



Ⅶ. CONCLUSIONS

This paper proposed a new voltage control scheme for an NLM operated MMC to develop both the output voltage and line-to-line voltage THD, and to achieve the maximum level of the output voltage. The proposed method keeps the advantages of the traditional voltage control scheme such as easy implementation and low switching loss. In addition, it avoids the disadvantages of existing methods such as increased THD, increased voltage level, complex calculations, topology complexity, etc.

Moreover, for the MMC itself, the proposed technique offers an easy numerical algorithm for the MMC topology that can be used with any number of sub-modules per arm either experimentally or by simulation. The usefulness of the proposed scheme was evaluated with MATLAB simulations with 30 SMs per arm. The benefits of the proposed method were verified under different experiment conditions and the obtained results matched well with the design expectation. Moreover, the proposed scheme showed a promising application potential in MMCs.



ACKNOWLEDGMENT

This research was supported by Korea Electric Power Corporation (Grant number: R17XA05-18).



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[8] Z. Li, P. Wang, H. Zhu, and Y. Li, “An improved pulse width modulation method for chopper-cell-based modular multilevel converters,” IEEE Trans. Power Electron., Vol. 27, No. 8, pp. 3472-3481, Aug. 2012.

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[13] Y. Liu, H. Hong, and A. Q. Huang, “Real-time algorithm for minimizing THD in multilevel inverters with unequal or varying voltage steps under staircase modulation,” IEEE Trans. Ind. Electron., Vol. 56, No. 6, pp. 2249-2258, Jun. 2009.

[14] B. Han, B. Bae, S. Baek, and G. Jang, “Dynamic characteristics analysis of SSSC based on multibridge inverter,” IEEE Trans. Power Del., Vol. 17, No. 2, pp. 623-629, Apr. 2002.

[15] S. Yashwant and A. Nampally, “Modular multilevel converter modulation using fundamental switching selective harmonic elimination method,” IEEE ICRERA, pp. 736-741, Nov. 2016.

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[17] K. Sharifabadi, Design, Control, and Application of Modular Multilevel Converters for HVDC Transmission Systems, IEEE Press/Wiley, 2016.

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Devnath Anupom received his B.S. degree in Electrical and Electronic Engineering from the Chittagong University of Engineering and Technology, Chittagong, Bangladesh, in 2017. He is presently working towards his M.S. degree at Hongik University, Seoul, Korea. His current research interests include MMCs for HVDC systems and power conversion systems for renewable energy source.


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Dong-Cheol Shin received his B.S. and M.S. degrees in Electrical Engineering from Hongik University, Seoul, Korea, in 2017 and 2019, respectively, where he is presently working towards his Ph.D. degree. His current research interests include MMCs for HVDC systems and power conversion systems for renewable energy sources.


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Dong-Myung Lee received his B.S. and M.S. degrees in Electrical Engineering from Hanyang University, Seoul, Korea, in 1994 and 1996, respectively. He received his Ph.D. degree in Electrical and Computer Engineering from the Georgia Institute of Technology, Atlanta, GA, USA, in 2004. From 1996 to 2000, he worked for LG Electronics Inc., Seoul, Korea. From 2004 to 2007, he was employed as a Senior Engineer at the Samsung SDI R&D Center, Yongin, Korea. From 2007 to 2008, he was a Research Professor in the Department of Electrical Engineering, Hanyang University. Since 2008, he has been a Professor in the School of Electronic and Electrical Engineering, Hongik University, Seoul, Korea. His current research interests include multi-level converters, variable speed drives, power quality compensation devices, power conversion systems for renewable energy sources and personal mobility.