Improved CB‑PWM strategy to reduce capacitor voltage errors for five‑level nested neutral point clamped inverters

Thuong Hoai Tran; Khoa Dang Pham; Nho-Van Nguyen

Improved CB‑PWM strategy to reduce capacitor voltage errors for five‑level nested neutral point clamped inverters

Thuong Hoai Tran

Khoa Dang Pham

Nho-Van Nguyen

Vol. 25, No. 12, pp. 2214-2225, Dec. 2025

10.1007/s43236-025-01048-8

Capacitor voltage balancing control

Carrier-based pulse-width modulation

Nested neutral point clamped inverter

Abstract

This article presents a carrier-based pulse-width modulation strategy (CB-PWM) with improved voltage balancing control (VBC4) for five-level nested-neutral-point-clamped inverters. Similar to other voltage balancing controls, VBC4 is based on the principle of minimized stored capacitor energy. In particular, VBC4 involves a comparison among three flying capacitors in each phase leg to determine the one with the maximum absolute voltage ripple. It then selects the best switching state to minimize the stored energy of this maximum-absolute-voltage-ripple capacitor. If two redundant states lead to the same minimum stored energy of a maximum-deviation capacitor, the two remaining capacitors are taken into consideration. In particular, the redundant state resulting in the smallest stored energy of a second-maximum-deviation capacitor is selected. Based on simulation and experimental results, VBC4 yields a reduction of the voltage ripple of the two inner flying capacitors in each phase leg in the medium–high modulation range while still maintaining the outer flying capacitors at an acceptable level of voltage ripple (< 5%). In addition, VBC4 gives a significant reduction in the RMS capacitor currents for the whole modulation range. Thus, the capacitor losses are reduced and the capacitor lifetime is extended.

Statistics

Show / Hide Statistics

Cumulative Counts from September 30th, 2019
Multiple requests among the same browser session are counted as one view. If you mouse over a chart, the values of data points will be shown.

Cite this article

[IEEE Style]

T. H. Tran, K. D. Pham, N. Nguyen, "Improved CB‑PWM strategy to reduce capacitor voltage errors for five‑level nested neutral point clamped inverters," Journal of Power Electronics, vol. 25, no. 12, pp. 2214-2225, 2025. DOI: 10.1007/s43236-025-01048-8.

[ACM Style]

Thuong Hoai Tran, Khoa Dang Pham, and Nho-Van Nguyen. 2025. Improved CB‑PWM strategy to reduce capacitor voltage errors for five‑level nested neutral point clamped inverters. Journal of Power Electronics, 25, 12, (2025), 2214-2225. DOI: 10.1007/s43236-025-01048-8.