Improved device characteristics in 4H‑SiC UMOSFETs with high‑κ HfO2/SiO2 stacking gates

This paper introduces a novel stacked trench transistor (S-UMOSFET) that significantly enhances blocking voltage and switching efficiency compared to conventional UMOSFETs. Traditional designs suffer from SiO2 gate oxide failures due to electric field crowding at trench corners and its limited dielectric strength. The S-UMOSFET addresses this problem with a unique HfO2/SiO2 stacked gate oxide layer that reduces the peak electric field and redistributes voltage stress while suppressing leakage currents. In addition, the device reliability of the S-UMOSFET structure under high temperatures (175 °C) and dual-pulse switching is studied. Results show that the overall performance of S-UMOSFET devices are significantly enhanced, demonstrating that the S-UMOSFET is an excellent choice for application in power devices.

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Cite this article

[IEEE Style]

W. Wu, B. Zhang, Y. Zhang, Y. Wang, J. Hu, X. Luo, X. Deng, H. Chen, Y. Zheng, "Improved device characteristics in 4H‑SiC UMOSFETs with high‑κ HfO2/SiO2 stacking gates," Journal of Power Electronics, vol. 26, no. 1, pp. 181-189, 2026. DOI: 10.1007/s43236-025-01058-6.

[ACM Style]

Weijie Wu, Bangmin Zhang, Yuyang Zhang, Yu Wang, Jiahao Hu, Xin Luo, Xiaochuan Deng, Hongbo Chen, and Yue Zheng. 2026. Improved device characteristics in 4H‑SiC UMOSFETs with high‑κ HfO2/SiO2 stacking gates. Journal of Power Electronics, 26, 1, (2026), 181-189. DOI: 10.1007/s43236-025-01058-6.