A novel PLL technique using digital lock-in amplifier under distorted grid conditions

Muhammad Noman Ashraf; Reyyan Ahmad Khan; Abdul Shakoor Akram; Woojin Choi

A novel PLL technique using digital lock-in amplifier under distorted grid conditions

Muhammad Noman Ashraf

Reyyan Ahmad Khan

Abdul Shakoor Akram

Woojin Choi

Vol. 26, No. 4, pp. 818-830, Apr. 2026

10.1007/s43236-025-01252-6

Grid-connected inverters

DC offset

Lock-in amplifier

Phase-locked loops

Abstract

IEEE Standards 519 and P1547 enforce strict limits on the harmonics, phase, and frequency variation in grid-connected inverter outputs. Optimally designed phase-locked loops (PLLs) are essential for synchronizing inverters with the grid to satisfy these standards. Various PLL methods have been proposed, but their performances are degraded in the presence of DC offsets and grid harmonics. This paper proposes a novel digital lock-in amplifier PLL (DLA-PLL) to address these challenges. The DLA-PLL utilizes a robust phase-sensitive detector (PSD), making it immune to harmonics and DC offsets except at the fundamental frequency. Simulations and experiments demonstrate the superiority of the proposed DLA-PLL over six conventional PLL methods under highly distorted grid conditions and power-quality events.

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Cite this article

[IEEE Style]

M. N. Ashraf, R. A. Khan, A. S. Akram, W. Choi, "A novel PLL technique using digital lock-in amplifier under distorted grid conditions," Journal of Power Electronics, vol. 26, no. 4, pp. 818-830, 2026. DOI: 10.1007/s43236-025-01252-6.

[ACM Style]

Muhammad Noman Ashraf, Reyyan Ahmad Khan, Abdul Shakoor Akram, and Woojin Choi. 2026. A novel PLL technique using digital lock-in amplifier under distorted grid conditions. Journal of Power Electronics, 26, 4, (2026), 818-830. DOI: 10.1007/s43236-025-01252-6.