A New Overlap Current Restraining Method for Current-source Rectifier

To ensure a DC current path and avoid large voltage overshoot of the DC-link inductor, alternating PWM pulses in the current-source rectifier should be supplemented by overlap time, which generates an overlap current and causes input current distortion. In this study, the influence of overlap time is illustrated by comparing the AC-side current before and after overlap time is added. The overlap current distribution caused by overlap time is discussed under different modulation carriers, including triangle carrier, positive-going carrier, and negative-going carrier. The quantitative relationship between the extra harmonics of the AC-side current and overlap time is based on the Fourier analysis. Based on the commutation analysis, a new carrier modulation scheme that can restrain overlap current is proposed. A 3 kW prototype is established to verify the effectiveness of the influence of overlap time and the proposed restraining modulation scheme.

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Cite this article

[IEEE Style]

H. Qin, Q. Liu, Y. Zhang, X. Zhang, D. Wang, "A New Overlap Current Restraining Method for Current-source Rectifier," Journal of Power Electronics, vol. 18, no. 2, pp. 615-626, 2018. DOI: 10.6113/JPE.2018.18.2.615.

[ACM Style]

Haihong Qin, Qing Liu, Ying Zhang, Xin Zhang, and Dan Wang. 2018. A New Overlap Current Restraining Method for Current-source Rectifier. Journal of Power Electronics, 18, 2, (2018), 615-626. DOI: 10.6113/JPE.2018.18.2.615.