Capacitance Estimation of the Submodule Capacitors in Modular Multilevel Converters for HVDC Applications


Vol. 16, No. 5, pp. 1752-1762, Sep. 2016
10.6113/JPE.2016.16.5.1752


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 Abstract

To achieve higher reliability in the modular multilevel converters (MMC) for HVDC transmission systems, the internal condition of the DC capacitors of the submodules (SM) needs to be monitored regularly. For an online estimation of the SM capacitance, a controlled AC current with double the fundamental frequency is injected into the circulating current loop of the MMC, which results in current and voltage ripples in the SM capacitors. The capacitor currents are calculated from the arm currents and their switching states. By processing these AC voltage and current components with digital filters, their capacitances are estimated by a recursive least square (RLS) algorithm. The validity of the proposed scheme has been verified by simulation results for a 300-MW, 300-kV HVDC system. In addition, its feasibility has been verified by experimental results obtained with a reduced-scale prototype. It has been shown that the estimation errors for both the simulation and experimental tests are 1.32% at maximum.


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Cite this article

[IEEE Style]

Y. Jo, T. H. Nguyen and D. Lee, "Capacitance Estimation of the Submodule Capacitors in Modular Multilevel Converters for HVDC Applications," Journal of Power Electronics, vol. 16, no. 5, pp. 1752-1762, 2016. DOI: 10.6113/JPE.2016.16.5.1752.

[ACM Style]

Yun-Jae Jo, Thanh Hai Nguyen, and Dong-Choon Lee. 2016. Capacitance Estimation of the Submodule Capacitors in Modular Multilevel Converters for HVDC Applications. Journal of Power Electronics, 16, 5, (2016), 1752-1762. DOI: 10.6113/JPE.2016.16.5.1752.