Selective Harmonic Elimination for a Single-Phase 13-level TCHB Based Cascaded Multilevel Inverter Using FPGA

Wahidah Abd. Halim; Nasrudin Abd. Rahim; Maaspaliza Azri

Selective Harmonic Elimination for a Single-Phase 13-level TCHB Based Cascaded Multilevel Inverter Using FPGA

Wahidah Abd. Halim

Nasrudin Abd. Rahim

Maaspaliza Azri

Vol. 14, No. 3, pp. 488-498, May 2014

10.6113/JPE.2014.14.3.488

Field-Programmable Gate Array (FPGA)

Multilevel inverter

Pulse-width modulation

Total harmonic distortion (THD)

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Abstract

This paper presents an implementation of selective harmonic elimination (SHE) modulation for a single-phase 13-level transistor-clamped H-bridge (TCHB) based cascaded multilevel inverter. To determine the optimum switching angle of the SHE equations, the Newton-Raphson method is used in solving the transcendental equation describing the fundamental and harmonic components. The proposed SHE scheme used the relationship between the angles and a sinusoidal reference waveform based on voltage-angle equal criteria. The proposed SHE scheme is evaluated through simulation and experimental results. The digital modulator based-SHE scheme using a field-programmable gate array (FPGA) is described and has been implemented on an Altera DE2 board. The proposed SHE is efficient in eliminating the 3rd, 5th, 7th, 9th and 11th order harmonics, which validates the analytical results. From the results, it can be seen that the adopted 13-level inverter produces a higher quality with a better harmonic profile and sinusoidal shape of the stepped output waveform.

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Cite this article

[IEEE Style]

W. A. Halim, N. A. Rahim, M. Azri, "Selective Harmonic Elimination for a Single-Phase 13-level TCHB Based Cascaded Multilevel Inverter Using FPGA," Journal of Power Electronics, vol. 14, no. 3, pp. 488-498, 2014. DOI: 10.6113/JPE.2014.14.3.488.

[ACM Style]

Wahidah Abd. Halim, Nasrudin Abd. Rahim, and Maaspaliza Azri. 2014. Selective Harmonic Elimination for a Single-Phase 13-level TCHB Based Cascaded Multilevel Inverter Using FPGA. Journal of Power Electronics, 14, 3, (2014), 488-498. DOI: 10.6113/JPE.2014.14.3.488.