Digital Controller Candidate for Point-of-load Synchronous Buck Converter in Tri-mode Mechanism

Li-mei Xiu; Wei-ping Zhang; Bo Li; Yuan-sheng Liu

Digital Controller Candidate for Point-of-load Synchronous Buck Converter in Tri-mode Mechanism

Vol. 14, No. 4, pp. 796-805, Jul. 2014

10.6113/JPE.2014.14.4.796

CMOS integrated circuit

DC?DC converter

Digital control

Digital pulse width modulator

System on-chip

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Abstract

A digital controller with a low-power approach for point-of-load synchronous buck converters is discussed and compared with its analog counterpart to confirm its feasibility for system integration. The tri-mode digital controller IC in 0.35 μm CMOS process is presented to demonstrate solutions that include a PID, quarter PID, and robust RST compensators. These compensators address the steady-state, stand-by, and transient modes according to the system operating point. An idle-tone free condition for S?D DPWM reduces the inherent tone noise under DC-excitation. Compared with that of the traditional approach, this condition generates a quasi-pure modulation signal. Experimental results verify the closed-loop performances and confirm the power-saving mechanism of the proposed controller.

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Cite this article

[IEEE Style]

L. Xiu, W. Zhang, B. Li, Y. Liu, "Digital Controller Candidate for Point-of-load Synchronous Buck Converter in Tri-mode Mechanism," Journal of Power Electronics, vol. 14, no. 4, pp. 796-805, 2014. DOI: 10.6113/JPE.2014.14.4.796.

[ACM Style]

Li-mei Xiu, Wei-ping Zhang, Bo Li, and Yuan-sheng Liu. 2014. Digital Controller Candidate for Point-of-load Synchronous Buck Converter in Tri-mode Mechanism. Journal of Power Electronics, 14, 4, (2014), 796-805. DOI: 10.6113/JPE.2014.14.4.796.