Parallel PCS Interconnection Current Surge Elimination Technique Using a Coupled Inductor
Vol. 14, No. 5, pp. 827-833, Sep. 2014
10.6113/JPE.2014.14.5.827
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Cite this article
[IEEE Style]
J. Choe, B. Byen, G. Choe, "Parallel PCS Interconnection Current Surge Elimination Technique Using a Coupled Inductor," Journal of Power Electronics, vol. 14, no. 5, pp. 827-833, 2014. DOI: 10.6113/JPE.2014.14.5.827.
[ACM Style]
Jung-Muk Choe, Byeng-Joo Byen, and Gyu-Ha Choe. 2014. Parallel PCS Interconnection Current Surge Elimination Technique Using a Coupled Inductor. Journal of Power Electronics, 14, 5, (2014), 827-833. DOI: 10.6113/JPE.2014.14.5.827.