Modulation method of parallel interleaved three‑level inverter considering neutral point potential and phase current balance

Ying Zhong; Weichao Li; Liang Zhou; Chen Deng; Jinyang Han

Modulation method of parallel interleaved three‑level inverter considering neutral point potential and phase current balance

Vol. 23, No. 2, pp. 241-251, Feb. 2023

10.1007/s43236-022-00568-x

Five-level space vector

Parallel interleaved

Meticulous partition

Voltage ripple

Abstract

The capacity and equivalent switching frequency of parallel interleaved inverters can be increased, but there are problems with neutral point potential balance and parallel bridge circulating current. This paper regards the parallel three-level inverter as a five-level inverter and five-level space vector integrated modulation is applied. On this basis, a neutral-point potential control strategy based on the mid-point charge to calculate the adjustment factor k is proposed. By further meticulously partitioning specific sector regions, the selection method of redundant vectors in the switching sequence is optimized without increasing the switching times, and the midpoint voltage ripple is reduced. Then, the redundant state allocation in the process of splitting the five-level into three-level is used as a new degree of freedom to suppress the circulating current of the parallel bridge, therefore realizing the control of voltage and current sharing. Finally, simulation and experiments verify the correctness and effectiveness of the method.

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Cite this article

[IEEE Style]

Y. Zhong, W. Li, L. Zhou, C. Deng, J. Han, "Modulation method of parallel interleaved three‑level inverter considering neutral point potential and phase current balance," Journal of Power Electronics, vol. 23, no. 2, pp. 241-251, 2023. DOI: 10.1007/s43236-022-00568-x.

[ACM Style]

Ying Zhong, Weichao Li, Liang Zhou, Chen Deng, and Jinyang Han. 2023. Modulation method of parallel interleaved three‑level inverter considering neutral point potential and phase current balance. Journal of Power Electronics, 23, 2, (2023), 241-251. DOI: 10.1007/s43236-022-00568-x.