Development of a Switched Diode Asymmetric Multilevel Inverter Topology

D. Karthikeyan; Vijayakumar Krishnasamy; Mohd. Ali Jagabar Sathik

Development of a Switched Diode Asymmetric Multilevel Inverter Topology

D. Karthikeyan

Vijayakumar Krishnasamy

Mohd. Ali Jagabar Sathik

Vol. 18, No. 2, pp. 418-431, Mar. 2018

10.6113/JPE.2018.18.2.418

Asymmetric cascaded multilevel inverter

Nearest level modulation

Reduced switches

Total harmonic distortion

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Abstract

This paper presents a new asymmetrical multilevel inverter with a reduced number of power electronic components. The proposed multilevel inverter is analyzed using two different configurations: i) First Configuration (with a switched diode) and ii) Second Configuration (without a switched diode). The presented topologies are compared with recent multilevel inverter topologies in terms of number of switches, gate driver circuits and blocking voltages. The proposed topologies can be cascaded to generate the maximum number of output voltage levels and they are suitable for high voltage applications. Various power quality issues are addressed for both of the configurations. The proposed 11-level inverter configuration is simulated using MATLAB and it is validated with a laboratory based experimental setup.

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Cite this article

[IEEE Style]

D. Karthikeyan, V. Krishnasamy, M. A. J. Sathik, "Development of a Switched Diode Asymmetric Multilevel Inverter Topology," Journal of Power Electronics, vol. 18, no. 2, pp. 418-431, 2018. DOI: 10.6113/JPE.2018.18.2.418.

[ACM Style]

D. Karthikeyan, Vijayakumar Krishnasamy, and Mohd. Ali Jagabar Sathik. 2018. Development of a Switched Diode Asymmetric Multilevel Inverter Topology. Journal of Power Electronics, 18, 2, (2018), 418-431. DOI: 10.6113/JPE.2018.18.2.418.