Analysis and Implementation of High Step-Up DC/DC Convertor with Modified Super-Lift Technique

Rezvan Fani; Ebrahim Farshidi; Ehsan Adib; Abdolnabi Kosarian

Analysis and Implementation of High Step-Up DC/DC Convertor with Modified Super-Lift Technique

Vol. 19, No. 3, pp. 645-654, May 2019

10.6113/JPE.2019.19.3.645

Coupled inductor

DC-DC convertors

High step up converter

Non-isolated technique

Super-lift technique

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Abstract

In this paper, a new high step up DC/DC converter with a modified super-lift technique is presented. The coupled inductor technique is combined with the super-lift technique to provide a tenfold or more voltage gain with a proper duty cycle and a low turn ratio. Due to a high conversion ratio, the voltage stress on the semiconductor devices is reduced. As a result, low voltage ultra-fast recovery diodes and low on resistance MOSFET can be used, which improves the reverse recovery problems and conduction losses. This converter employs a passive clamp circuit to recycle the energy stored in the leakage inductance. The proposed convertor features a high conversion ratio with a low turn ratio, low voltage stress, low reverse recovery losses, omission of the inrush currents of the switch capacitor loops, high efficiency, small volume and reduced cost. This converter is suitable for renewable energy applications. The operational principle and a steady-state analysis of the proposed converter are presented in details. A 200W, 30V input, 380V output laboratory prototype circuit is implemented to confirm the theoretical analysis.

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Cite this article

[IEEE Style]

R. Fani, E. Farshidi, E. Adib, A. Kosarian, "Analysis and Implementation of High Step-Up DC/DC Convertor with Modified Super-Lift Technique," Journal of Power Electronics, vol. 19, no. 3, pp. 645-654, 2019. DOI: 10.6113/JPE.2019.19.3.645.

[ACM Style]

Rezvan Fani, Ebrahim Farshidi, Ehsan Adib, and Abdolnabi Kosarian. 2019. Analysis and Implementation of High Step-Up DC/DC Convertor with Modified Super-Lift Technique. Journal of Power Electronics, 19, 3, (2019), 645-654. DOI: 10.6113/JPE.2019.19.3.645.