Influence of Parasitic Parameters on Switching Characteristics and Layout Design Considerations of SiC MOSFETs

Haihong Qin; Ceyu Ma; Ziyue Zhu; Yangguang Yan

Influence of Parasitic Parameters on Switching Characteristics and Layout Design Considerations of SiC MOSFETs

Vol. 18, No. 4, pp. 1255-1267, Jul. 2018

10.6113/JPE.2018.18.4.1255

Layout design

Parasitic capacitance

Parasitic inductance

Silicon Carbide (SiC)

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Abstract

Parasitic parameters have a larger influence on Silicon Carbide (SiC) devices with an increase of the switching frequency. This limits full utilization of the performance advantages of the low switching losses in high frequency applications. By combining a theoretical analysis with a experimental parametric study, a mathematic model considering the parasitic inductance and parasitic capacitance is developed for the basic switching circuit of a SiC MOSFET. The main factors affecting the switching characteristics are explored. Moreover, a fast-switching double pulse test platform is built to measure the individual influences of each parasitic parameters on the switching characteristics. In addition, guidelines are revealed through experimental results. Due to the limits of the practical layout in the high-speed switching circuits of SiC devices, the matching relations are developed and an optimized layout design method for the parasitic inductance is proposed under a constant length of the switching loop. The design criteria are concluded based on the impact of the parasitic parameters. This provides guidelines for layout design considerations of SiC-based high-speed switching circuits.

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Cite this article

[IEEE Style]

H. Qin, C. Ma, Z. Zhu, Y. Yan, "Influence of Parasitic Parameters on Switching Characteristics and Layout Design Considerations of SiC MOSFETs," Journal of Power Electronics, vol. 18, no. 4, pp. 1255-1267, 2018. DOI: 10.6113/JPE.2018.18.4.1255.

[ACM Style]

Haihong Qin, Ceyu Ma, Ziyue Zhu, and Yangguang Yan. 2018. Influence of Parasitic Parameters on Switching Characteristics and Layout Design Considerations of SiC MOSFETs. Journal of Power Electronics, 18, 4, (2018), 1255-1267. DOI: 10.6113/JPE.2018.18.4.1255.