A Wide Input Range, 95.4% Power Efficiency DC-DC Buck Converter with a Phase-Locked Loop in 0.18 μm BCD

This paper presents a DC-DC buck converter with a Phase-Locked Loop (PLL) that can compensates for power efficiency degradation over a wide input range. Its switching frequency is kept at 2 MHz and the delay difference between the High side driver and the Low side driver can be minimized with respect to Process, Voltage and Temperature (PVT) variations by adopting the PLL. The operation mode of the proposed DC-DC buck converter is automatically changed to Pulse Width Modulation (PWM) or PWM frequency modes according to the load condition (heavy load or light load) while supporting a maximum load current of up to 1.2 A. The PWM frequency mode is used to extend the CCM region under the light load condition for the PWM operation. As a result, high efficiency can be achieved under the light load condition by the PWM frequency mode and the delay compensation with the PLL. The proposed DC-DC buck converter is fabricated with a 0.18 μm BCD process, and the die area is 3.96 mm2. It is implemented to have over a 90 % efficiency at an output voltage of 5 V when the input range is between 8 V and 20 V. As a result, the variation in the power efficiency is less than 1 % and the maximum efficiency of the proposed DC-DC buck converter with the PLL is 95.4 %.

Statistics

Show / Hide Statistics

Cumulative Counts from September 30th, 2019
Multiple requests among the same browser session are counted as one view. If you mouse over a chart, the values of data points will be shown.

Cite this article

[IEEE Style]

H. Kim, Y. Park, J. Park, H. Ryu, Y. Pu, M. Lee, K. Hwang, Y. Yang, K. Lee, "A Wide Input Range, 95.4% Power Efficiency DC-DC Buck Converter with a Phase-Locked Loop in 0.18 μm BCD," Journal of Power Electronics, vol. 16, no. 6, pp. 2024-2034, 2016. DOI: 10.6113/JPE.2016.16.6.2024.

[ACM Style]

Hongjin Kim, Young-Jun Park, Ju-Hyun Park, Ho-Cheol Ryu, Young-Gun Pu, Minjae Lee, Keumcheol Hwang, Younggoo Yang, and Kang-Yoon Lee. 2016. A Wide Input Range, 95.4% Power Efficiency DC-DC Buck Converter with a Phase-Locked Loop in 0.18 μm BCD. Journal of Power Electronics, 16, 6, (2016), 2024-2034. DOI: 10.6113/JPE.2016.16.6.2024.