A Hybrid Filtering Stage Based Quasi-type-1 PLL under Distorted Grid Conditions

Yunlu Li; Dazhi Wang; Wei Han; Zhenao Sun; Tianqing Yuan

A Hybrid Filtering Stage Based Quasi-type-1 PLL under Distorted Grid Conditions

Vol. 17, No. 3, pp. 704-715, May 2017

10.6113/JPE.2019.17.3.704

Moving average filter

Phase locked loop

Synchronization

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Abstract

For three-phase synchronization applications, the synchronous reference frame phase-locked loop (SRF-PLL) is probably the most widely used technique due to its ease of implementation and satisfactory phase tracking performance under ideal grid conditions. However, under unbalanced and distorted grid conditions, its performance tends to worsen. To deal with this problem, a variety of filtering stages have been proposed and used in SRF-PLLs for the rejection of disturbance components at the cost of degrading the dynamic performance. In this paper, to improve dynamic performance without compromising the filtering capability, an effective hybrid filtering stage is proposed and incorporated into the inner loop of a quasi-type-1 PLL (QT1-PLL). The proposed filtering stage is a combination of a moving average filter (MAF) and a modified delay signal cancellation (DSC) operator in cascade. The time delay caused by the proposed filtering stage is smaller than that in the conventional MAF-based and DSC-based PLLs. A small-signal model of the proposed PLL is derived. The stability is analyzed and parameters design guidelines are given. The effectiveness of the proposed PLL is confirmed through experimental results.

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Cite this article

[IEEE Style]

Y. Li, D. Wang, W. Han, Z. Sun, T. Yuan, "A Hybrid Filtering Stage Based Quasi-type-1 PLL under Distorted Grid Conditions," Journal of Power Electronics, vol. 17, no. 3, pp. 704-715, 2017. DOI: 10.6113/JPE.2019.17.3.704.

[ACM Style]

Yunlu Li, Dazhi Wang, Wei Han, Zhenao Sun, and Tianqing Yuan. 2017. A Hybrid Filtering Stage Based Quasi-type-1 PLL under Distorted Grid Conditions. Journal of Power Electronics, 17, 3, (2017), 704-715. DOI: 10.6113/JPE.2019.17.3.704.