Design and Verification of Improved Cascaded Multilevel Inverter Topology with Asymmetric DC Sources

Tarmizi Tarmizi; Soib Taib; M. K. Mat Desa

Design and Verification of Improved Cascaded Multilevel Inverter Topology with Asymmetric DC Sources

Tarmizi Tarmizi

Soib Taib

M. K. Mat Desa

Vol. 19, No. 5, pp. 1074-1086, Sep. 2019

https://doi.org/10.6113/JPE.2019.19.5.1074

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Abstract

This paper presents the design and implementation of an improved cascaded multilevel inverter topology with asymmetric DC sources. This experimental inverter topology is a stand-alone system with simulations and experiments performed using resistance loads. The topology uses four asymmetric binary DC sources that are independent from each other and one H-bridge. The topology was simulated using PSIM software before an actual prototype circuit was tested. The proposed topology was shown to be very efficient. It was able to generate a smooth output waveform up to 31 levels with only eight switches. The obtained simulation and experimental results are almost identical. In a 1,200W (48.3) resistive load application, the THDv and efficiency of the topology were found to be 1.7% and 97%, respectively. In inductive load applications, the THDv values were 1.1% and 1.3% for an inductive load (R=54 dan L=146mH) and a 36W fluorescent lamp load with a capacitor connected at the dc bus.

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Cite this article

[IEEE Style]

T. Tarmizi, S. Taib, M. K. M. Desa, "Design and Verification of Improved Cascaded Multilevel Inverter Topology with Asymmetric DC Sources," Journal of Power Electronics, vol. 19, no. 5, pp. 1074-1086, 2019. DOI: https://doi.org/10.6113/JPE.2019.19.5.1074.

[ACM Style]

Tarmizi Tarmizi, Soib Taib, and M. K. Mat Desa. 2019. Design and Verification of Improved Cascaded Multilevel Inverter Topology with Asymmetric DC Sources. Journal of Power Electronics, 19, 5, (2019), 1074-1086. DOI: https://doi.org/10.6113/JPE.2019.19.5.1074.